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Visitor pcross
Registered: ‎11-14-2018

Interfacing HLS AXIS with AXI Stream Data Fifos

I'm having a problem with interfacing an HLS block to the AXI4-Stream Data Fifo. Specifically I need the HLS axis slave to perform a non blocking read (in some capacity) but I cannot get this behaviour to work. I've pasted a portion of my HLS code below which synths with an interval of 1 and simulates without problem. (In simulation READY always is set before VALID which I'm not sure how I could adapt my code to block read 1 cycle before data appears when I have no mechanism for knowing data is coming besides VALID).


#pragma HLS INTERFACE ap_ctrl_hs port=return
#pragma HLS INTERFACE axis port=S_AXIS_port_in #pragma HLS PIPELINE static ap_axiu_10G pkt_storageBuffer1[BUFFER_SIZE*ETH_MTU]; #pragma HLS STREAM variable=pkt_storageBuffer1 if(S_AXIS_port_in.read_nb(port1_read)){ pkt_storageBuffer1[pkt_storageGlobal] = port1_read; pkt_storageGlobal = pkt_storageGlobal+1==BUFFER_SIZE*ETH_MTU ? 0 : pkt_storageGlobal+1; pkt_storageLocal++; if(port1_read.last){ pkt_queued++; pkt_storageLocal=0; } } } //Some other code that must run even if the non blocking read does not occur. Shares the pkt_storageBuffer1

So I took this HLS and placed it in a block design, connected the slave axis interface to the output of an axi4-stream data fifo in packet mode and... nothing. Well specifically I run it through an ILA and find that the TREADY signal from my slave interface is just holding 0 constantly. If I change this to just .read instead of .read_nb data flows through this block but as I stated I have code below that must run either way and .read will lock the entire block down because the fifo has no data to provide (all based on what I see in UG902).


I've tried altering this approach a few different ways, splitting valid, switch to ap_fifo instead, or keep track of valid last clock cycle but none function as I desire. I eventually found this in UG1037 "The READY slave output cannot be generated combinatorially from the VALID slave input....Alternatively, READY can be registered and driven in the cycle following the VALID assertion". So I now see why I can't just splice valid from the Fifo into my HLS code but what am I supposed to do? If I use a static variable and set READY based on the last clock cycles valid assertion (as suggested by UG1037) at some point the Fifo will hit TLAST=1 (because I am in packet mode) and there is no gurantee more data is in the Fifo. At that point my read would block but there is that code below which I cannot block.


Anyone who can help point out what I assume is an obvious mistake on my part I would be extremely grateful.

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