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Visitor prasathec
Visitor
185 Views
Registered: ‎11-19-2018

Interfacing Vivado HLS (IP) block in Vivado design

Hello,

I have used Vivado HLS to design a top function which accepts 4 input (uint8, uint8, uint16, uint16) and produces 4 outputs (all of uint32). I have optimized the design, used axilite interface with bundle (peripheral interface) and followed UG871 Vivado design suite tutorial to test the design in hardware using SDK.

But the design goal is to process each set of inputs every 16ns in a  Zynq Ultrascale+ ZCU102 kit. In Vivado HLS, I have used 10ns clock cycle with pure pipelined architecture. After synthesis, I made sure the interval is 1, with latency being a least point of interest (Latency - 31). I have the following queries, because of which I could not able to proceed further.

1. Although synthesis results in an interval of 1, RTL Co-simulation results in an interval of 2. I did not understand that why there is a deviation between synthesis and co-simulation results. What will be the impact of this when it is implemented in PL? I have used AXIS interface for all the inputs and outputs. Default ports such as ap_clk, ap_rst_n, ap_start and ap_ready are mapped to ap_ctrl_hs protocol.

2. For Axilite - peripheral bus interface, UG871 tutorial was very helpful to implement the design in Vivado (2018.3) and to test the design in SDK. But with the axis interfaces in HLS IP block, I am struggling to connect the HLS designed IP to Zynq MPSoC in Vivado tool. What is the AXI Interconnect I should use in Vivado to realise the connection between HLS IP and Zynq MPSoC?

3. With the solution to the above questions and once after programming the bit stream in FPGA, how can I test the same with SDK? For Axilite there are some driver functions out of HDL wrapper, through which the arguments/inputs can be passed to PL (UG871 has an overview of that). But for AXIS port how could I pass the input to PL? I suppose, how can I code in SDK to write and read data (Set/Get)? Any suggestion(s) or tutorial(s) on this would be very helpful.

Many thanks in advance!

Best,

Prasath

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Moderator
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Registered: ‎05-31-2017

Re: Interfacing Vivado HLS (IP) block in Vivado design

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