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Scholar xilinxacct
Scholar
235 Views
Registered: ‎10-23-2018

Is HLS ‘uncertainty’ associated only with the ‘clock’?

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In HLS, in the solution configuration, you can specify the ‘uncertainty’. The GUI implies this is associated with just the clock.

Is this truly a factor of just the clock? (e.g. jitter, skew, …)

OR

is it related to out of context/propagation in general… i.e. If you had a pure combinational logic, would the uncertainty be (near) 0, and the time estimates would be (close to) accurate?

Thanks

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Moderator
Moderator
188 Views
Registered: ‎10-04-2011

Re: Is HLS ‘uncertainty’ associated only with the ‘clock’?

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I would just add on to @evant_nq's response and say that HLS provides initial estimates of the logic resources and delays, but can not account for the physical synthesis optimizations of the RTL synthesis in Vivado. For this reason, it is always recommended to export the IP with at least the Vivado synthesis process run. This will provide accurate resource utilization and better timing estimates. Final design timing will still be dependent on total FPGA resource utilization as routing delays in a congested design can become a significant portion of the total delay. 

2 Replies
Explorer
Explorer
196 Views
Registered: ‎07-18-2018

Re: Is HLS ‘uncertainty’ associated only with the ‘clock’?

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Hi xilinxacct,

   If you go to page 29 in UG902 : https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug902-vivado-high-level-synthesis.pdf:

"Uncertainty: The clock period used for synthesis is the clock period minus the clock uncertainty. Vivado HLS uses internal models to estimate the delay of the operations for each FPGA. The clock uncertainty value provides a controllable margin to account for any increases in net delays due to RTL logic synthesis, place, and route. If not specified in nanoseconds (ns) or a percentage, the clock uncertainty defaults to 12.5% of the clock period."

Which I think is able to answer your question. Basically the number you put in is going to be subtracted from the period when synthesis is done for the clock to give a user electable amount of margin.

 

 

Moderator
Moderator
189 Views
Registered: ‎10-04-2011

Re: Is HLS ‘uncertainty’ associated only with the ‘clock’?

Jump to solution

I would just add on to @evant_nq's response and say that HLS provides initial estimates of the logic resources and delays, but can not account for the physical synthesis optimizations of the RTL synthesis in Vivado. For this reason, it is always recommended to export the IP with at least the Vivado synthesis process run. This will provide accurate resource utilization and better timing estimates. Final design timing will still be dependent on total FPGA resource utilization as routing delays in a congested design can become a significant portion of the total delay.