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Registered: ‎05-30-2018

Making use of ap_ctrl_chain

Hello everyone,

My project consists of a top function that calls a number of sub-functions as a stream under dataflow.

each sub-function represents a computation block that performs a certain task. I also have DMA for input and output in order to convert axilite (memory mapped) to axi stream and vice versa.

It looks something like :

TOP : [MM2S --> StreamBlock 1 --> StreamBlock  2 --> ... --> StreamBlock n --> S2MM]

Each time, I have to wait for the data to pass through the whole stream before the next input can be applied.

I would like to speed up the stream by making use of ap_ctrl_chain, so that whenever a block is done processing, a flag signal is sent out.

  1. Is it enough to add ap_ctrl_chain to the return port interface of the top level function? or should I synthesize each sub-function separately and use ap_ctrl_chain for it?

  2. In case I would like to synthesize each sub_function separately, do I have to specify the interface type and bundle for the function's arguments? Only the MM2S and S2MM of the DMA are actually going to be interfacing the PS using axilite.

  3. These sub-functions are using some global arrays as coefficients for calculations. Is it still possible for the separate blocks to access global arrays defined elsewhere somehow? or should they be made local in this case?

  4. Any other suggestions please?

Thank you so much !

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2 Replies
Xilinx Employee
Xilinx Employee
Registered: ‎09-05-2018

Re: Making use of ap_ctrl_chain

Hey @rashedkoutayni,

The dataflow directive should be telling the synthesizer to pipeline the sub-functions, and it's my understanding that it does this by inferring the ap_ctrl_chain directive on those sub-functions. So you shouldn't have to do this explicitly..

But there does seem to be some reason why HLS couldn't pipeline the dataflow region. Are there any dataflow warnings in the console? Can you use the dataflow viewer and the information in UG902 to debug why your functions aren't being pipelined?

Nicholas Moellers

Xilinx Worldwide Technical Support
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Registered: ‎05-30-2018

Re: Making use of ap_ctrl_chain

Hey @nmoeller,

Thank you for your answer !

First of all, I noticed that when I add the directives of :

#pragma HLS interface ap_ctrl_chain port=return bundle=CRTL_BUS

then the protocol of the following RTL Ports is changed from ap_ctrl_hs to ap_ctrl_chain for every sub-function (saw it in synthesis report) :

ap_clk, ap_rst, ap_start, start_full_n, ap_ready, ap_done, ap_continue, ap_idle, start_out, start_write .

Secondly, the only thing I got in the log is that dataflow is applied to the top function, and that the process function(s) were detected/extracted. Looks like it is applied correctly.

But this means that the sub-functions are pipelined with each others, but not the whole design for the input. Please let me explain by the following example:

A top-level function takes an image as input and does some image processing on it, by calling 10 sub-functions. These 10 functions are pipelined with each others, and this is good.

But what I would like to do is to be able to feed the top-level function with a 2nd image even before the 1st image is done processing, because the first part of the top pipeline is empty (i.e. done processing the 1st image). say only 4 sub-functions are left for the 1st image, while the other 6 sub-functions are actually idle.

Even I don't know how to feed the 2nd image as input before the top-function call from PS returns.

How to utilize the idle sub-functions for the next input? and how to call the PL correctly from the PS ?

Sorry for long explanation, I hope you got my point :)

Thank you so much !

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