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Adventurer
Adventurer
5,281 Views
Registered: ‎12-18-2012

Memory interface property OTHER in an HLS IP incompatible with BRAM controller

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The memory interfaces created for an array input in an HLS IP have a configuration property of OTHER when imported in the IP integrator. The BRAM controller on the other hand has an interface with a BRAM_CTRL property. This causes validation and synthesis unable to complete successfully.

 

When I try to validate the design I get this critical warning in the IP integrator:

 

 [BD 41-237] Bus Interface property MASTER_TYPE does not match between /IO_network_0_bram/BRAM_PORTA(BRAM_CTRL) and /IO_network_0/IniArray_axonPar_PORTA(OTHER)

 

These properties cannot be changed in the IP integrator (grayed out). Is there way to make the 2 BRAM interfaces compatible in HLS? 

Otherwise how are we supposed to use memory intefaces in an HLS in an IP integrator design? Is there another option than using the BRAM controller?

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Adventurer
Adventurer
8,693 Views
Registered: ‎12-18-2012

Re: Memory interface property OTHER in an HLS IP incompatible with BRAM controller

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NeverMind..There was probalbly some glitch..When i re-imported the IP the property was not grayed out anymore...

 

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Highlighted
Adventurer
Adventurer
8,694 Views
Registered: ‎12-18-2012

Re: Memory interface property OTHER in an HLS IP incompatible with BRAM controller

Jump to solution

NeverMind..There was probalbly some glitch..When i re-imported the IP the property was not grayed out anymore...

 

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