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Observer pp_dsp
Observer
5,652 Views
Registered: ‎09-12-2013

Register ap_memory interface

Dear HLS folks,

 

I have decreased the clock period from 4 ns to 2 ns to examine the limitations of my design.

The experience is the following: the maximum frequency of the design is limited by the delay of the memory 'load' operation.

I think this delay is related to an unregistered memory estimation (Virtex 7).

 

Can I define that the memory resource has to be registered? If yes, how?

Even highes binding and scheduling efforts does not influence this.

 

 

"@W [SCHED-21] Estimated delay (2.39ns) of 'load' operation ('x_l_re_im_i_mapped_load', fft_hls_top.h:213->fft_radix2_wrapper.cpp:41) on array 'x_l_re_im_i_mapped' exceeds the target cycle time (target cycle time: 2ns, clock uncertainty: 0.25ns, effective cycle time: 1.75ns)."

 

 

Thanks in advance,

Balazs

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3 Replies
Xilinx Employee
Xilinx Employee
5,614 Views
Registered: ‎08-17-2011

Re: Register ap_memory interface

Hello Balazs,

 

I think this is a delay model that the tool has for accessing the BRAM.

 

If I'm not too mistaken, it looks like this is the delay for one of the registers signals to be clocked into the BRAM - in other words, if you register everything and in the best possible situation, the critical path is still 2.39 ns.

 

I'm not a very good datasheet reader... Please check table 31 of DS 183:

http://www.xilinx.com/support/documentation/data_sheets/ds183_Virtex_7_Data_Sheet.pdf

 

If you want to try further tests, in UG902, there is a description of how to force a register; it's also included in an header file from the tool, so the example usage would be:

 

#include <hls/utils/x_hls_utils.h>

top ( .... int array[DIM] ...) ... array should be mapped as ap_memory

 

change from : int temp = array(index);

change to : int temp = reg ( array( reg(index) ) ) ;

 

As you can guess this would register the read address index and register the read back data from the external memory.

 

However I really think you are reaching for the maximum values of the BRAM timing here.

 

I hope this helps, please let the community know your feedback.

- Hervé

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Observer pp_dsp
Observer
5,590 Views
Registered: ‎09-12-2013

Re: Register ap_memory interface

Hello herver,

thanks for your answer.

 

The false path reported by HLS don't contain other delays, only this 2.39 ns. If I see alright, this means I have reached the frequency limitation caused by the BRAM already. I thought that I can reach higher frequencyes with the V7-2 (the referenced sheet present higher frequency values as well.).

 

The register trick presented above does not influence this BRAM phenomenon, but helped a lot in other cases, so I'm very grateful for it. Thanks! :)

 

Balazs

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Moderator
Moderator
5,565 Views
Registered: ‎04-17-2011

Re: Register ap_memory interface

Hello Balazs,

Please feel free to mark the answer which had help you as an Accepted Solution for other members.
Regards,
Debraj
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