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Visitor bevan1
Visitor
560 Views
Registered: ‎10-11-2014

Reported function latency off by one

Hi,

 

I have found an inconsistency between the reported latency of a function and the actual latency of the generated HDL module. For functions with a latency >1 cycles, the generated HDL takes one cycle more than reported. Following is a simple demonstation:

 

int add(int x, int y) {
#pragma HLS LATENCY min=N max=N
#pragma HLS INLINE off
#pragma HLS PIPELINE
	return x + y;
}

int top(int x, int y) {
	return add(x, y);
}

N is varied between 0 and 3 in the following and we have a look at the HLS report and the generated Verilog for "add".

 

N=0

  • Report for add: Latency 0, II 1
  • Report for top: Latency 0
  • Verilog module for "add" is purely combinatorial

N=1

  • Report for add: Latency 1, II 1
  • Report for top: Latency 1
  • Verilog module for "add" now contains one output register stage

N=2

  • Report for add: Latency 2, II 1
  • Report for top: Latency 3 (!)
  • Verilog module for "add" now contains two output register stages and additionally buffers the inputs, i.e. it takes three cycles from input to output

N=3

  • Report for add: Latency 3, II 1
  • Report for top: Latency 4
  • Verilog module for "add" adds another output register stage, so it now takes four cycles from input to output

 

So, the interesting step here is from N=1 to N=2 where two additional register stages are introduced into the HDL code. HLS obviously knows about this and the number of cycles required by "top" increases by two. I tested this with Vivado HLS 2018.1. The generated Verilog code is attached to this post.

 

Is there a reason for this behavior or is it a bug? I would expect the generated module to take as many cycles as requested using the "HLS LATENCY" pragma and as stated in the HLS report.

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2 Replies
Xilinx Employee
Xilinx Employee
441 Views
Registered: ‎05-06-2008

Re: Reported function latency off by one

Hello @bevan1,

 

I am looking into this issue and I will keep  you posted.

 

Thanks,
Chris

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Xilinx Employee
Xilinx Employee
429 Views
Registered: ‎05-06-2008

Re: Reported function latency off by one

Hello @bevan1,

 

I have reproduced the issue and I have filed a change request with the developers.

 

It appears that the PIPELINE directive is adding an additional register on the latency gets above two.  When I removed this directive, the latency matches the expected results.

 

Good Luck,
Chris