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Explorer
Explorer
487 Views
Registered: ‎10-09-2014

Severe DATAPACK bug found in 2017.4

Hi,

 

I believe I have found a bug with DATAPACK on a interface with type stream<struct>. I have created a project as attached in case any of you want to reproduce the error. I run it with Vivado 2017.4 in Ubuntu 16.04. You will see dependency error in cosim if you run "vivado_hls -f script.tcl". I understand there may be some limitation about cosim, however, if you check the generated code, you can see that the data ports of the internal fifo are tied to 0, which means it is impossible to store any input data at all. I have found it working if I:

 

1) comment out all DATAPACK pragma in the code

2) use non-struct type

3) copy moveTo and rename it to moveTo1, and replace one of the moveTo with moveTo1.

 

Here is the synthesizable code:

 

struct Somestruct

{

ap_uint<8> a;

ap_uint<8> b;

};

 

void moveTo(hls::stream<SomeStruct>& i_data, hls::stream<SomeStruct>& o_data)
{
#pragma HLS INLINE off
#pragma HLS PIPELINE II=1

if (! i_data.empty())
{
o_data.write(i_data.read());
}
}

void data_pack_test(hls::stream<SomeStruct>& i_data, hls::stream<SomeStruct>& o_data)
{
#pragma HLS DATAFLOW
#pragma HLS INTERFACE axis port=i_data
#pragma HLS INTERFACE axis port=o_data
#pragma HLS DATA_PACK variable=i_data
#pragma HLS DATA_PACK variable=o_data

 

static hls::stream<SomeStruct> int_data;
#pragma HLS STREAM variable=int_data depth=16 dim=1
#pragma HLS DATA_PACK variable=int_data

 

moveTo(i_data, int_data);
moveTo(int_data, o_data);
}

 

Thanks,

Jimmy

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2 Replies
443 Views
Registered: ‎03-09-2018

Re: Severe DATAPACK bug found in 2017.4

Hi!

I have found this in Vivado HLS user guide, maybe it can help you.

 

Moreover, you could trie to use an ap_uint<16> instead of a struct and check if it works. Of course, in this case you have to manually access the two 8-bit fields within the 16-bit value.

Screen Shot 2018-03-13 at 9.10.16 AM.png
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Explorer
Explorer
429 Views
Registered: ‎10-09-2014

Re: Severe DATAPACK bug found in 2017.4

Hi @emanuele.delsozzo,

 

Thanks for the reply. Your link just proves that my code is supported in cosimulation, note the words "but not two or more". 

 

Anyway, cosim is just a way to help Xilinx employee to reproduce the problem, the real project is that the synthesized function results in wrong HDL and  does not work in hardware. Here is the internal fifo part of synthesized verilog. You can clearly see that the data port is tied to 0, so there is no chance to work. You can also write your own test bench to test it.

 

fifo_w24_d16_A int_data_V_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(24'd0),
.if_full_n(int_data_V_r_full_n),
.if_write(1'b0),
.if_dout(int_data_V_r_dout),
.if_empty_n(int_data_V_r_empty_n),
.if_read(1'b0)
);

 

Thanks,

Jimmy

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