04-15-2018 12:11 PM
Apologize for the newbie question.
Let's assume I have the following subfunction (invoked from the top module):
void skip_samples( const uint16_t N, const uint16_t M, int32_t *in, volatile int32_t *out )
where in is an ap_fifo and out is memory-mapped via a AXI master interface.
The goal is the following:
So, in summary, we need to read N+M+N from in, and write only N+N to out. I understand that out could easily be an ap_fifo as well, but due to the top-level design, it must be AXI-Master memory-mapped.
I seem to have troubles with the "skipping" part. I tried two different design, one based upon for loops, another via memcpy( ), and both hang the board (testbenches work well). On the other hand, interestingly, if I do some sort of explicit processing of the M samples to be skipped (for example, computing a checksum), the module works well. What am I missing?
04-16-2018 03:52 AM
My two cents in your question in ap_fifo input :
- If the array is accessed in a sequential manner an ap_fifo interface can be used.
- So, I don't see how you skip M samples. Does it break the above rule of FIFO object in HLS ?