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Visitor thibautm
Visitor
865 Views
Registered: ‎10-19-2017

Unable to build C/RTL cosimulation executable with SDx 2018.2: compilation fails

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Hello,

I am not able to build a C/RTL co-simulation executable with SDx 2018.2.
I just installed it on a fresh-installed Ubuntu 16.04.3 VM (one of the supported Linux distributions).
Note that synthesis or C simulation runs fine.


I attach the Vivado HLS log file containing the errors from gcc.
For short, the first error is (I added the equivalent I got from clang, more explicit):

/opt/Xilinx/Vivado/2018.2/tps/lnx64/gcc-6.2.0/include/c++/6.2.0/cstdlib:184:10: error: expected unqualified-id before ‘__int128’
/opt/Xilinx/Vivado/2018.2/tps/lnx64/gcc-6.2.0/include/c++/6.2.0/cstdlib:185:7: error: __int128 is not supported on this target

Note that the compilation is done for a 32-bit ABI (-m32 flag).

 

 


Steps for reproduce:

  • create sample project within SDx for array_zero_copy
  • change the sources by the files attached in src.zip (that pull apart main from accelerator code)
  • build it
  • launch Vivado HLS from SDx
  • add test bench (main.c)
  • run C/RTL Co-simulation


More information:

$ uname -a
Linux sdx2 4.10.0-28-generic #32~16.04.2-Ubuntu SMP Thu Jul 20 10:19:48 UTC 2017 x86_64 x86_64 x86_64 GNU/Linux


Co-simulation executable build command lines (from the directory Debug/_sds/vhls/array_zero_copy/solution/sim/wrapc):

$ make -f cosim.tv.mk -n | grep -v echo
if /opt/Xilinx/Vivado/2018.2/tps/lnx64/gcc-6.2.0/bin/g++ -fPIC -g -I "/opt/Xilinx/Vivado/2018.2/include" -I "/opt/Xilinx/Vivado/2018.2/include/ap_sysc" -I "/opt/Xilinx/Vivado/2018.2/common/technology/generic/SystemC" -I "/opt/Xilinx/Vivado/2018.2/common/technology/generic/SystemC/AESL_FP_comp" -I "/opt/Xilinx/Vivado/2018.2/common/technology/generic/SystemC/AESL_comp" -I "/opt/Xilinx/Vivado/2018.2/lnx64/tools/systemc/include" -I "/opt/Xilinx/Vivado/2018.2/lnx64/tools/auto_cc/include" -I "/usr/include/x86_64-linux-gnu" -D__SIM_FPO__ -D__SIM_OPENCV__ -D__SIM_FFT__ -D__SIM_FIR__ -D__SIM_DDS__ -D__DSP48E1__ -Wno-unknown-pragmas -I/home/user/workspace/test-cosim/src -I/opt/Xilinx/SDx/2018.2/target/aarch32-linux/include -I/home/user/workspace/test-cosim/Debug -Wall -O0 -g -fmessage-length=0 -m32 -w -D__RTL_SIMULATION__ -D__xilinx_ip_top= -I . -I "/opt/Xilinx/Vivado/2018.2/lnx64/tools/systemc/include" -I "/opt/Xilinx/Vivado/2018.2/include" -I "/opt/Xilinx/Vivado/2018.2/common/technology/generic/SystemC/AESL_comp"   -DC_TEST -DSST_SIM_ENABLE -DSST_ATBG_ENABLE   -D_DEBUG  -fpermissive  -c -DAESL_PIPELINE -MD -MT obj/apatb_array_zero_copy.o -MP -MF obj/apatb_array_zero_copy.CXXd apatb_array_zero_copy.cpp -o obj/apatb_array_zero_copy.o ; \
then mv -f "obj/apatb_array_zero_copy.CXXd" "obj/apatb_array_zero_copy.d"; \
else rm -f "obj/apatb_array_zero_copy.CXXd"; exit 1; fi
/opt/Xilinx/Vivado/2018.2/tps/lnx64/gcc-6.2.0/bin/gcc    -fno-builtin-isinf -fno-builtin-isnan -c -fPIC -g -I "/opt/Xilinx/Vivado/2018.2/include" -I "/opt/Xilinx/Vivado/2018.2/include/ap_sysc" -I "/opt/Xilinx/Vivado/2018.2/common/technology/generic/SystemC" -I "/opt/Xilinx/Vivado/2018.2/common/technology/generic/SystemC/AESL_FP_comp" -I "/opt/Xilinx/Vivado/2018.2/common/technology/generic/SystemC/AESL_comp" -I "/opt/Xilinx/Vivado/2018.2/lnx64/tools/systemc/include" -I "/opt/Xilinx/Vivado/2018.2/lnx64/tools/auto_cc/include" -I "/usr/include/x86_64-linux-gnu" -D__SIM_FPO__ -D__SIM_OPENCV__ -D__SIM_FFT__ -D__SIM_FIR__ -D__SIM_DDS__ -D__DSP48E1__ -Wno-unknown-pragmas -I/home/user/workspace/test-cosim/src -I/opt/Xilinx/SDx/2018.2/target/aarch32-linux/include -I/home/user/workspace/test-cosim/Debug -Wall -O0 -g -fmessage-length=0 -m32 -w -D__RTL_SIMULATION__ -D__xilinx_ip_top= -I . -I "/opt/Xilinx/Vivado/2018.2/lnx64/tools/systemc/include" -I "/opt/Xilinx/Vivado/2018.2/include" -I "/opt/Xilinx/Vivado/2018.2/common/technology/generic/SystemC/AESL_comp" -DAESL_PIPELINE array_zero_copy.cpp_pre.cpp.tb.cpp -o obj/array_zero_copy.cpp_pre.cpp.tb.o; \

/opt/Xilinx/Vivado/2018.2/tps/lnx64/gcc-6.2.0/bin/gcc    -fno-builtin-isinf -fno-builtin-isnan -c -fPIC -g -I "/opt/Xilinx/Vivado/2018.2/include" -I "/opt/Xilinx/Vivado/2018.2/include/ap_sysc" -I "/opt/Xilinx/Vivado/2018.2/common/technology/generic/SystemC" -I "/opt/Xilinx/Vivado/2018.2/common/technology/generic/SystemC/AESL_FP_comp" -I "/opt/Xilinx/Vivado/2018.2/common/technology/generic/SystemC/AESL_comp" -I "/opt/Xilinx/Vivado/2018.2/lnx64/tools/systemc/include" -I "/opt/Xilinx/Vivado/2018.2/lnx64/tools/auto_cc/include" -I "/usr/include/x86_64-linux-gnu" -D__SIM_FPO__ -D__SIM_OPENCV__ -D__SIM_FFT__ -D__SIM_FIR__ -D__SIM_DDS__ -D__DSP48E1__ -Wno-unknown-pragmas -I/home/user/workspace/test-cosim/src -I/opt/Xilinx/SDx/2018.2/target/aarch32-linux/include -I/home/user/workspace/test-cosim/Debug -Wall -O0 -g -fmessage-length=0 -m32 -w -D__RTL_SIMULATION__ -D__xilinx_ip_top= -I . -I "/opt/Xilinx/Vivado/2018.2/lnx64/tools/systemc/include" -I "/opt/Xilinx/Vivado/2018.2/include" -I "/opt/Xilinx/Vivado/2018.2/common/technology/generic/SystemC/AESL_comp" -DAESL_PIPELINE main.cpp_pre.cpp.tb.cpp -o obj/main.cpp_pre.cpp.tb.o; \

/opt/Xilinx/Vivado/2018.2/tps/lnx64/gcc-6.2.0/bin/g++ obj/apatb_array_zero_copy.o obj/array_zero_copy.cpp_pre.cpp.tb.o obj/main.cpp_pre.cpp.tb.o -D_DEBUG -L "/opt/Xilinx/Vivado/2018.2/lnx64/tools/systemc/lib" -lsystemc -lpthread -Wl,--as-needed -Wl,-rpath,"/opt/Xilinx/Vivado/2018.2/lnx64/tools/systemc/lib" -L "/opt/Xilinx/Vivado/2018.2/lnx64/tools/systemc/lib" -lsystemc -lpthread -Wl,-rpath,"/opt/Xilinx/Vivado/2018.2/lnx64/lib/csim" -L "/opt/Xilinx/Vivado/2018.2/lnx64/lib/csim" -lhlsmc++-GCC46 -fno-builtin -fno-inline -Wl,-rpath,"/opt/Xilinx/Vivado/2018.2/lnx64/lib/csim" -L "/opt/Xilinx/Vivado/2018.2/lnx64/lib/csim" -lhlsm-GCC46 -Wl,-rpath,"/opt/Xilinx/Vivado/2018.2/lnx64/tools/fpo_v7_0" -L "/opt/Xilinx/Vivado/2018.2/lnx64/tools/fpo_v7_0" -lgmp -lmpfr -lIp_floating_point_v7_0_bitacc_cmodel -Wl,-rpath,"/opt/Xilinx/Vivado/2018.2/lnx64/tools/opencv/opencv_gcc" -L "/opt/Xilinx/Vivado/2018.2/lnx64/tools/opencv/opencv_gcc" -lopencv_calib3d -lopencv_contrib -lopencv_core -lopencv_features2d -lopencv_flann -lopencv_gpu -lopencv_highgui -lopencv_imgproc -lopencv_legacy -lopencv_ml -lopencv_objdetect -lopencv_photo -lopencv_stitching -lopencv_superres -lopencv_ts -lopencv_video -lopencv_videostab -Wl,-rpath,"/opt/Xilinx/Vivado/2018.2/lnx64/tools/fft_v9_1" -L "/opt/Xilinx/Vivado/2018.2/lnx64/tools/fft_v9_1" -lIp_xfft_v9_1_bitacc_cmodel -Wl,-rpath,"/opt/Xilinx/Vivado/2018.2/lnx64/tools/fir_v7_0" -L "/opt/Xilinx/Vivado/2018.2/lnx64/tools/fir_v7_0" -lgmp -lIp_fir_compiler_v7_2_bitacc_cmodel -Wl,-rpath,"/opt/Xilinx/Vivado/2018.2/lnx64/tools/dds_v6_0" -L "/opt/Xilinx/Vivado/2018.2/lnx64/tools/dds_v6_0" -lIp_dds_compiler_v6_0_bitacc_cmodel  -o cosim.tv.exe

The failing command is the compilation of main.cpp_pre.cpp.tb.cpp.


Commands issued after the fresh Ubuntu installation, as required by the documentation :

dpkg --add-architecture i386
apt-get update
apt-get install libc6:i386 libncurses5:i386 libstdc++6:i386
apt-get install g++-multilib
apt-get install libgtk2.0-0:i386 dpkg-dev:i386
ln -s /usr/bin/make /usr/bin/gmake


Does anyone have an idea on what I am doing wrong ?

Thank you,

Thibaut

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1 Solution

Accepted Solutions
Visitor thibautm
Visitor
442 Views
Registered: ‎10-19-2017

Re: Unable to build C/RTL cosimulation executable with SDx 2018.2: compilation fails

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Hello,

I solved the problem. In fact, cosimulation does not seem to be supported (or even tested) in the SDSoC flow.

You can reproduce the bug with SDSoC GUI (very simple broken flow that most users would try):

  1. create simple SDSoC project, with two files: one with HW function and one with a main function working as a test bench (example sources are in attached tarball)
  2. build the project, kill it after a while (we just need SDSoC to create the Vivado HLS project)
  3. launch Vivado HLS on the HW function from the GUI
  4. add the file with the main function as test bench
  5. (run synthesis or C simulation, everything works well)
  6. launch cosimulation: fails

Resulting error:

(...)
INFO: [COSIM 212-14] Instrumenting C test bench ...
   Build using "/opt/Xilinx/Vivado/2018.2/tps/lnx64/gcc-6.2.0/bin/g++"
   Compiling apatb_fmac.cpp
   Compiling (apcc) fmac.c_pre.c.tb.c
ERROR: /opt/Xilinx/Vivado/2018.2/tps/lnx32/jre does not exist.
ERROR: Could not find 32-bit executable.
ERROR: /opt/Xilinx/Vivado/2018.2/bin/unwrapped/lnx32.o/apcc does not exist
ERROR: -m32 switch is not supported.
make: *** [obj/fmac.c_pre.c.tb.o] Error 1
ERROR: [COSIM 212-317] C++ compile error.
ERROR: [COSIM 212-321] EXE file generate failed.
ERROR: [COSIM 212-321] EXE file generate failed.
ERROR: [COSIM 212-331] Aborting co-simulation: C simulation failed, compilation errors.
command 'ap_source' returned error code
    while executing
"source /path/to/Debug/_sds/vhls/fmac/solution/cosim.tcl"
    invoked from within
"hls::main /path/to/Debug/_sds/vhls/fmac/solution/cosim.tcl"
    ("uplevel" body line 1)
    invoked from within
"uplevel 1 hls::main {*}$args"
    (procedure "hls_proc" line 5)
    invoked from within
"hls_proc $argv"
Finished C/RTL cosimulation.

Note the "ERROR: -m32 switch is not supported." line.

You can reproduce the bug without GUI (what I usually do: I let SDSoC generate Vivado HLS project and tcl files and edit the tcl file to add test bench and cosimulation):

  1. download and extract attached tarball
  2. run make

Resulting error:

(...)
ERROR: /opt/Xilinx/Vivado/2018.2/tps/lnx32/jre does not exist.
ERROR: Could not find 32-bit executable.
ERROR: /opt/Xilinx/Vivado/2018.2/bin/unwrapped/lnx32.o/apcc does not exist
ERROR: -m32 switch is not supported.
(...)

This "-m32" flag can be removed from CFLAGS in the generated fmac_run.tcl (Vivado HLS tcl files) by using sdscc argument (see Makefile's first lines):

-hls-target-flags " "

Removing it does not impact usual compilation and linking (run `make fmac` to see), the final binary if for the right architecture (ARM

Note that the sdscc argument:

-hls-target 1

makes thing even worst. You get this error:

gcc: error: unrecognized command line option ‘-target’; did you mean ‘-ftarget=’

 

Furthermore, it is not possible to add test bench files from the sdscc invokation, nor to enable cosimulation, but it is easy to add it to the tcl files or in the Vivado HLS GUI, leading to those errors.

That would be great to add in order to improve debugging/reliability when using SDSoC flow.

 

Note that the same problem and solution applies to SDSoC 2018.3.

3 Replies
Xilinx Employee
Xilinx Employee
828 Views
Registered: ‎05-06-2008

Re: Unable to build C/RTL cosimulation executable with SDx 2018.2: compilation fails

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Hello @thibautm,

 

I noticed in the gcc command line that it has a '-m32' option used, but the OS is 64 bit. Can you remove this option and re-run the make file?

 

Thanks,
Chris

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Visitor thibautm
Visitor
815 Views
Registered: ‎10-19-2017

Re: Unable to build C/RTL cosimulation executable with SDx 2018.2: compilation fails

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Hello @chrisz.

 

I guess Vivado HLS added this flag on purpose as I choose the zc706 target that have 32-bit ARM processors.

If I remove it and run again the compilation (after a clean) I get:

 

   Build using "/opt/Xilinx/Vivado/2018.2/tps/lnx64/gcc-6.2.0/bin/g++"
   Compiling apatb_array_zero_copy.cpp
   Compiling array_zero_copy.cpp_pre.cpp.tb.cpp
In file included from /opt/Xilinx/Vivado/2018.2/tps/lnx64/gcc-6.2.0/include/c++/6.2.0/ext/new_allocator.h:33:0,
                 from /opt/Xilinx/Vivado/2018.2/tps/lnx64/gcc-6.2.0/include/c++/6.2.0/x86_64-pc-linux-gnu/32/bits/c++allocator.h:33,
                 from /opt/Xilinx/Vivado/2018.2/tps/lnx64/gcc-6.2.0/include/c++/6.2.0/bits/allocator.h:46,
                 from /opt/Xilinx/Vivado/2018.2/tps/lnx64/gcc-6.2.0/include/c++/6.2.0/string:41,
                 from /opt/Xilinx/Vivado/2018.2/tps/lnx64/gcc-6.2.0/include/c++/6.2.0/bits/locale_classes.h:40,
                 from /opt/Xilinx/Vivado/2018.2/tps/lnx64/gcc-6.2.0/include/c++/6.2.0/bits/ios_base.h:41,
                 from /opt/Xilinx/Vivado/2018.2/tps/lnx64/gcc-6.2.0/include/c++/6.2.0/ios:42,
                 from /opt/Xilinx/Vivado/2018.2/tps/lnx64/gcc-6.2.0/include/c++/6.2.0/ostream:38,
                 from /opt/Xilinx/Vivado/2018.2/tps/lnx64/gcc-6.2.0/include/c++/6.2.0/iostream:39,
                 from /home/user/workspace/test-cosim/src/array_zero_copy.cpp:42:
/opt/Xilinx/Vivado/2018.2/tps/lnx64/gcc-6.2.0/include/c++/6.2.0/new:117:41: error: ‘operator new’ takes type ‘size_t’ (‘long unsigned int’) as first parameter [-fpermissive]
   __attribute__((__externally_visible__));
                                         ^
/opt/Xilinx/Vivado/2018.2/tps/lnx64/gcc-6.2.0/include/c++/6.2.0/new:119:41: error: ‘operator new’ takes type ‘size_t’ (‘long unsigned int’) as first parameter [-fpermissive]
   __attribute__((__externally_visible__));
                                         ^
/opt/Xilinx/Vivado/2018.2/tps/lnx64/gcc-6.2.0/include/c++/6.2.0/new:131:41: error: ‘operator new’ takes type ‘size_t’ (‘long unsigned int’) as first parameter [-fpermissive]
   __attribute__((__externally_visible__));
                                         ^
/opt/Xilinx/Vivado/2018.2/tps/lnx64/gcc-6.2.0/include/c++/6.2.0/new:133:41: error: ‘operator new’ takes type ‘size_t’ (‘long unsigned int’) as first parameter [-fpermissive]
   __attribute__((__externally_visible__));
                                         ^
/opt/Xilinx/Vivado/2018.2/tps/lnx64/gcc-6.2.0/include/c++/6.2.0/new:146:51: error: ‘operator new’ takes type ‘size_t’ (‘long unsigned int’) as first parameter [-fpermissive]
 inline void* operator new(std::size_t, void* __p) _GLIBCXX_USE_NOEXCEPT
                                                   ^~~~~~~~
/opt/Xilinx/Vivado/2018.2/tps/lnx64/gcc-6.2.0/include/c++/6.2.0/new:148:53: error: ‘operator new’ takes type ‘size_t’ (‘long unsigned int’) as first parameter [-fpermissive]
 inline void* operator new[](std::size_t, void* __p) _GLIBCXX_USE_NOEXCEPT
                                                     ^~~~~~~~
In file included from /opt/Xilinx/Vivado/2018.2/tps/lnx64/gcc-6.2.0/include/c++/6.2.0/bits/range_access.h:36:0,
                 from /opt/Xilinx/Vivado/2018.2/tps/lnx64/gcc-6.2.0/include/c++/6.2.0/string:51,
                 from /opt/Xilinx/Vivado/2018.2/tps/lnx64/gcc-6.2.0/include/c++/6.2.0/bits/locale_classes.h:40,
                 from /opt/Xilinx/Vivado/2018.2/tps/lnx64/gcc-6.2.0/include/c++/6.2.0/bits/ios_base.h:41,
                 from /opt/Xilinx/Vivado/2018.2/tps/lnx64/gcc-6.2.0/include/c++/6.2.0/ios:42,
                 from /opt/Xilinx/Vivado/2018.2/tps/lnx64/gcc-6.2.0/include/c++/6.2.0/ostream:38,
                 from /opt/Xilinx/Vivado/2018.2/tps/lnx64/gcc-6.2.0/include/c++/6.2.0/iostream:39,
                 from /home/user/workspace/test-cosim/src/array_zero_copy.cpp:42:
/opt/Xilinx/Vivado/2018.2/tps/lnx64/gcc-6.2.0/include/c++/6.2.0/initializer_list:47:11: fatal error: definition of std::initializer_list does not match #include <initializer_list>
     class initializer_list
           ^~~~~~~~~~~~~~~~
compilation terminated.
cosim.tv.mk:68: recipe for target 'obj/array_zero_copy.cpp_pre.cpp.tb.o' failed
make: *** [obj/array_zero_copy.cpp_pre.cpp.tb.o] Error 1

 

The commands executed by make are:

 

$ make -f cosim.tv.mk -n | grep -v echo
if /opt/Xilinx/Vivado/2018.2/tps/lnx64/gcc-6.2.0/bin/g++ -fPIC -g -I "/opt/Xilinx/Vivado/2018.2/include" -I "/opt/Xilinx/Vivado/2018.2/include/ap_sysc" -I "/opt/Xilinx/Vivado/2018.2/common/technology/generic/SystemC" -I "/opt/Xilinx/Vivado/2018.2/common/technology/generic/SystemC/AESL_FP_comp" -I "/opt/Xilinx/Vivado/2018.2/common/technology/generic/SystemC/AESL_comp" -I "/opt/Xilinx/Vivado/2018.2/lnx64/tools/systemc/include" -I "/opt/Xilinx/Vivado/2018.2/lnx64/tools/auto_cc/include" -I "/usr/include/x86_64-linux-gnu" -D__SIM_FPO__ -D__SIM_OPENCV__ -D__SIM_FFT__ -D__SIM_FIR__ -D__SIM_DDS__ -D__DSP48E1__ -Wno-unknown-pragmas -I/home/user/workspace/test-cosim/src -I/opt/Xilinx/SDx/2018.2/target/aarch32-linux/include -I/home/user/workspace/test-cosim/Debug -Wall -O0 -g -fmessage-length=0 -w -D__RTL_SIMULATION__ -D__xilinx_ip_top= -I . -I "/opt/Xilinx/Vivado/2018.2/lnx64/tools/systemc/include" -I "/opt/Xilinx/Vivado/2018.2/include" -I "/opt/Xilinx/Vivado/2018.2/common/technology/generic/SystemC/AESL_comp" -DC_TEST -DSST_SIM_ENABLE -DSST_ATBG_ENABLE -D_DEBUG -fpermissive -c -DAESL_PIPELINE -MD -MT obj/apatb_array_zero_copy.o -MP -MF obj/apatb_array_zero_copy.CXXd apatb_array_zero_copy.cpp -o obj/apatb_array_zero_copy.o ; \ then mv -f "obj/apatb_array_zero_copy.CXXd" "obj/apatb_array_zero_copy.d"; \ else rm -f "obj/apatb_array_zero_copy.CXXd"; exit 1; fi /opt/Xilinx/Vivado/2018.2/tps/lnx64/gcc-6.2.0/bin/gcc -fno-builtin-isinf -fno-builtin-isnan -c -fPIC -g -I "/opt/Xilinx/Vivado/2018.2/include" -I "/opt/Xilinx/Vivado/2018.2/include/ap_sysc" -I "/opt/Xilinx/Vivado/2018.2/common/technology/generic/SystemC" -I "/opt/Xilinx/Vivado/2018.2/common/technology/generic/SystemC/AESL_FP_comp" -I "/opt/Xilinx/Vivado/2018.2/common/technology/generic/SystemC/AESL_comp" -I "/opt/Xilinx/Vivado/2018.2/lnx64/tools/systemc/include" -I "/opt/Xilinx/Vivado/2018.2/lnx64/tools/auto_cc/include" -I "/usr/include/x86_64-linux-gnu" -D__SIM_FPO__ -D__SIM_OPENCV__ -D__SIM_FFT__ -D__SIM_FIR__ -D__SIM_DDS__ -D__DSP48E1__ -Wno-unknown-pragmas -I/home/user/workspace/test-cosim/src -I/opt/Xilinx/SDx/2018.2/target/aarch32-linux/include -I/home/user/workspace/test-cosim/Debug -Wall -O0 -g -fmessage-length=0 -w -D__RTL_SIMULATION__ -D__xilinx_ip_top= -I . -I "/opt/Xilinx/Vivado/2018.2/lnx64/tools/systemc/include" -I "/opt/Xilinx/Vivado/2018.2/include" -I "/opt/Xilinx/Vivado/2018.2/common/technology/generic/SystemC/AESL_comp" -DAESL_PIPELINE array_zero_copy.cpp_pre.cpp.tb.cpp -o obj/array_zero_copy.cpp_pre.cpp.tb.o; \ /opt/Xilinx/Vivado/2018.2/tps/lnx64/gcc-6.2.0/bin/gcc -fno-builtin-isinf -fno-builtin-isnan -c -fPIC -g -I "/opt/Xilinx/Vivado/2018.2/include" -I "/opt/Xilinx/Vivado/2018.2/include/ap_sysc" -I "/opt/Xilinx/Vivado/2018.2/common/technology/generic/SystemC" -I "/opt/Xilinx/Vivado/2018.2/common/technology/generic/SystemC/AESL_FP_comp" -I "/opt/Xilinx/Vivado/2018.2/common/technology/generic/SystemC/AESL_comp" -I "/opt/Xilinx/Vivado/2018.2/lnx64/tools/systemc/include" -I "/opt/Xilinx/Vivado/2018.2/lnx64/tools/auto_cc/include" -I "/usr/include/x86_64-linux-gnu" -D__SIM_FPO__ -D__SIM_OPENCV__ -D__SIM_FFT__ -D__SIM_FIR__ -D__SIM_DDS__ -D__DSP48E1__ -Wno-unknown-pragmas -I/home/user/workspace/test-cosim/src -I/opt/Xilinx/SDx/2018.2/target/aarch32-linux/include -I/home/user/workspace/test-cosim/Debug -Wall -O0 -g -fmessage-length=0 -w -D__RTL_SIMULATION__ -D__xilinx_ip_top= -I . -I "/opt/Xilinx/Vivado/2018.2/lnx64/tools/systemc/include" -I "/opt/Xilinx/Vivado/2018.2/include" -I "/opt/Xilinx/Vivado/2018.2/common/technology/generic/SystemC/AESL_comp" -DAESL_PIPELINE main.cpp_pre.cpp.tb.cpp -o obj/main.cpp_pre.cpp.tb.o; \ /opt/Xilinx/Vivado/2018.2/tps/lnx64/gcc-6.2.0/bin/g++ obj/apatb_array_zero_copy.o obj/array_zero_copy.cpp_pre.cpp.tb.o obj/main.cpp_pre.cpp.tb.o -D_DEBUG -L "/opt/Xilinx/Vivado/2018.2/lnx64/tools/systemc/lib" -lsystemc -lpthread -Wl,--as-needed -Wl,-rpath,"/opt/Xilinx/Vivado/2018.2/lnx64/tools/systemc/lib" -L "/opt/Xilinx/Vivado/2018.2/lnx64/tools/systemc/lib" -lsystemc -lpthread -Wl,-rpath,"/opt/Xilinx/Vivado/2018.2/lnx64/lib/csim" -L "/opt/Xilinx/Vivado/2018.2/lnx64/lib/csim" -lhlsmc++-GCC46 -fno-builtin -fno-inline -Wl,-rpath,"/opt/Xilinx/Vivado/2018.2/lnx64/lib/csim" -L "/opt/Xilinx/Vivado/2018.2/lnx64/lib/csim" -lhlsm-GCC46 -Wl,-rpath,"/opt/Xilinx/Vivado/2018.2/lnx64/tools/fpo_v7_0" -L "/opt/Xilinx/Vivado/2018.2/lnx64/tools/fpo_v7_0" -lgmp -lmpfr -lIp_floating_point_v7_0_bitacc_cmodel -Wl,-rpath,"/opt/Xilinx/Vivado/2018.2/lnx64/tools/opencv/opencv_gcc" -L "/opt/Xilinx/Vivado/2018.2/lnx64/tools/opencv/opencv_gcc" -lopencv_calib3d -lopencv_contrib -lopencv_core -lopencv_features2d -lopencv_flann -lopencv_gpu -lopencv_highgui -lopencv_imgproc -lopencv_legacy -lopencv_ml -lopencv_objdetect -lopencv_photo -lopencv_stitching -lopencv_superres -lopencv_ts -lopencv_video -lopencv_videostab -Wl,-rpath,"/opt/Xilinx/Vivado/2018.2/lnx64/tools/fft_v9_1" -L "/opt/Xilinx/Vivado/2018.2/lnx64/tools/fft_v9_1" -lIp_xfft_v9_1_bitacc_cmodel -Wl,-rpath,"/opt/Xilinx/Vivado/2018.2/lnx64/tools/fir_v7_0" -L "/opt/Xilinx/Vivado/2018.2/lnx64/tools/fir_v7_0" -lgmp -lIp_fir_compiler_v7_2_bitacc_cmodel -Wl,-rpath,"/opt/Xilinx/Vivado/2018.2/lnx64/tools/dds_v6_0" -L "/opt/Xilinx/Vivado/2018.2/lnx64/tools/dds_v6_0" -lIp_dds_compiler_v6_0_bitacc_cmodel -o cosim.tv.exe

Note that if I change the target include's directory "aarch32-linux" by "x86", I get the same result.

 

Thanks,

Thibaut

 

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Visitor thibautm
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Registered: ‎10-19-2017

Re: Unable to build C/RTL cosimulation executable with SDx 2018.2: compilation fails

Jump to solution

Hello,

I solved the problem. In fact, cosimulation does not seem to be supported (or even tested) in the SDSoC flow.

You can reproduce the bug with SDSoC GUI (very simple broken flow that most users would try):

  1. create simple SDSoC project, with two files: one with HW function and one with a main function working as a test bench (example sources are in attached tarball)
  2. build the project, kill it after a while (we just need SDSoC to create the Vivado HLS project)
  3. launch Vivado HLS on the HW function from the GUI
  4. add the file with the main function as test bench
  5. (run synthesis or C simulation, everything works well)
  6. launch cosimulation: fails

Resulting error:

(...)
INFO: [COSIM 212-14] Instrumenting C test bench ...
   Build using "/opt/Xilinx/Vivado/2018.2/tps/lnx64/gcc-6.2.0/bin/g++"
   Compiling apatb_fmac.cpp
   Compiling (apcc) fmac.c_pre.c.tb.c
ERROR: /opt/Xilinx/Vivado/2018.2/tps/lnx32/jre does not exist.
ERROR: Could not find 32-bit executable.
ERROR: /opt/Xilinx/Vivado/2018.2/bin/unwrapped/lnx32.o/apcc does not exist
ERROR: -m32 switch is not supported.
make: *** [obj/fmac.c_pre.c.tb.o] Error 1
ERROR: [COSIM 212-317] C++ compile error.
ERROR: [COSIM 212-321] EXE file generate failed.
ERROR: [COSIM 212-321] EXE file generate failed.
ERROR: [COSIM 212-331] Aborting co-simulation: C simulation failed, compilation errors.
command 'ap_source' returned error code
    while executing
"source /path/to/Debug/_sds/vhls/fmac/solution/cosim.tcl"
    invoked from within
"hls::main /path/to/Debug/_sds/vhls/fmac/solution/cosim.tcl"
    ("uplevel" body line 1)
    invoked from within
"uplevel 1 hls::main {*}$args"
    (procedure "hls_proc" line 5)
    invoked from within
"hls_proc $argv"
Finished C/RTL cosimulation.

Note the "ERROR: -m32 switch is not supported." line.

You can reproduce the bug without GUI (what I usually do: I let SDSoC generate Vivado HLS project and tcl files and edit the tcl file to add test bench and cosimulation):

  1. download and extract attached tarball
  2. run make

Resulting error:

(...)
ERROR: /opt/Xilinx/Vivado/2018.2/tps/lnx32/jre does not exist.
ERROR: Could not find 32-bit executable.
ERROR: /opt/Xilinx/Vivado/2018.2/bin/unwrapped/lnx32.o/apcc does not exist
ERROR: -m32 switch is not supported.
(...)

This "-m32" flag can be removed from CFLAGS in the generated fmac_run.tcl (Vivado HLS tcl files) by using sdscc argument (see Makefile's first lines):

-hls-target-flags " "

Removing it does not impact usual compilation and linking (run `make fmac` to see), the final binary if for the right architecture (ARM

Note that the sdscc argument:

-hls-target 1

makes thing even worst. You get this error:

gcc: error: unrecognized command line option ‘-target’; did you mean ‘-ftarget=’

 

Furthermore, it is not possible to add test bench files from the sdscc invokation, nor to enable cosimulation, but it is easy to add it to the tcl files or in the Vivado HLS GUI, leading to those errors.

That would be great to add in order to improve debugging/reliability when using SDSoC flow.

 

Note that the same problem and solution applies to SDSoC 2018.3.