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Visitor alling.j
Registered: ‎03-26-2019

Understanding hs_err_pid#####.log file


I'm pretty new to HLS and need some help understanding why my synthesis isn't working.

For some background, I'm running Vivado HLS 2018.3 on Ubuntu 16.04. I'm currently trying to synthesize some gnuradio c++ code into Verilog to run on a ZedBoard development board. I'm just trying to synthesize a single gnuradio block currently. I didn't write the code, so I've been piecing through it making changes so it's synthesizeable.

So far I've removed all malloc, calloc, and free calls and replaced them with static arrays instantiated to the max size I will need. Since the block is a class, I've put the class definition inside of the top-level function that creates an instance of the class and calls the one function I really need. If there's anything obvious beyond this I should check feel free to let me know.

Beyond this, when I run the synthesis, I get the following output at the end of the console:

INFO: [HLS 200-10] Checking synthesizability ...
Stack dump:
0.    Running pass 'Pointer Array Geometry' on module '/home/project_name/.autopilot/db/a.g.1.bc'.
Abnormal program termination (11)
Please check '/home/project_name/hs_err_pid18858.log' for details
Finished C synthesis.

I've tried checking hs_err_pid18858.log to see what's going on, but I can't decipher what the problems are. Where could I look to figure out what the log file is trying to tell me?

I appreciate any guidance that can be given.

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Xilinx Employee
Xilinx Employee
Registered: ‎09-05-2018

Re: Understanding hs_err_pid#####.log file


Hey there, that log is just a stack dump; it looks like the synthesizeability check crashed. If you PM me the project archive, I can investigate the crash.

But for your specific scenario, another think to get rid of might be the 'new' keyword, if you're allocating an object of that class that way. That's a sneaky way port C++ code tries to use dynamic memory.

If you want to post your code, we might be able to guess at other reasons why the synthesizeability check.. ehm.. failed. :)

Nicholas Moellers

Xilinx Worldwide Technical Support