UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor mehmettukel
Visitor
7,213 Views
Registered: ‎08-29-2013

Vivado HLS SystemC HDL Co-Simulation (without synthesizing)

Jump to solution

Hi there,

I know it is possible with Vivado HLS to synthesize SystemC code into HDL and simulate it. How about simulating a VHDL module which I have written earlier with a SystemC testbench? Again, HDL module is not synthesized from SystemC code. Is it possible to do that?

 

Thanks.

Mehmet

0 Kudos
1 Solution

Accepted Solutions
Moderator
Moderator
11,371 Views
Registered: ‎04-17-2011

Re: Vivado HLS SystemC HDL Co-Simulation (without synthesizing)

Jump to solution
The short answer is that its not possible. You cannot add RTL files directly to HLS for co-simulation. The entry point would be to add C/C++/SystemC file in HLS.
Regards,
Debraj
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos
3 Replies
Moderator
Moderator
11,372 Views
Registered: ‎04-17-2011

Re: Vivado HLS SystemC HDL Co-Simulation (without synthesizing)

Jump to solution
The short answer is that its not possible. You cannot add RTL files directly to HLS for co-simulation. The entry point would be to add C/C++/SystemC file in HLS.
Regards,
Debraj
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos
Visitor mehmettukel
Visitor
7,174 Views
Registered: ‎08-29-2013

Re: Vivado HLS SystemC HDL Co-Simulation (without synthesizing)

Jump to solution

Thank you debrajr. But isn't it nice if Vivado HLS can do that. Maybe Xilinx can consider this in next releases.

 

 

0 Kudos
79 Views
Registered: ‎06-13-2019

Re: Vivado HLS SystemC HDL Co-Simulation (without synthesizing)

Jump to solution

How to synthesis or creating a project  using  systemc program into HDL using Vivado? Can you please share any document if you have?

0 Kudos