09-10-2013 11:38 PM
I'm bringing a simple divide core generated from Vivado HLS into System Generator. I have instantiated a 'Vivado HLS' block and pointed it at the correct solution. The blocks appears with the correct ports and the model will go through an 'update diagram' .
However when I hit Run and the system generator compilation happens I get an error on the Vivado HLS block:
WARNING:HDL Compiler:267 - "xlisim_divide_top.v" Line 1142: Cannot find port nonw on this module
ERROR:HDL COmpiler:25 - "xlisim_divide_top.v" Line 1148: Module <divider_top> does not have a port named <none>.
ERROR:Simulator:778 - Static elaboration of top level Verilog design unit(s) in library work failed.
There is indeed no port named 'none' in my design and i do not expect there to be one. Has any one seen this or similar issues before? Any suggestions for a fix?
09-11-2013 02:33 AM
It seems this is a version issue.
I was observing this error when using Vivado 2013.1 to generate a core for use in System Generator from ISE 14.3.
Tested with ISE 14.5 and the core works a treat.
09-18-2013 09:35 AM