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Voyager
Voyager
132 Views
Registered: ‎10-23-2018

WARNING(s) in Xilinx HLS ‘Coding Style Examples’

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In the following HLS ‘Coding Style Example’ files provided by Xilinx there are WARNINGS…
loop_max_bounds
array_mem_bottleneck
loop_imperfect
loop_pipeline
loop_sequential
loop_var
pointer_arith
pointer_array
pointer_basic
pointer_cast_native
pointer_double
pointer_multi
pointer_basic
sc_FIFO_port
types_global
types_composite

Since these are ‘Coding Style Examples’… it is ‘assumed’ these are examples people should follow.

1) Are some of these actually ‘bad examples’? (showing what not to do). If so, could you point those out?

2) Are these indicating that despite following the best practices, these warnings will occur anyway? (e.g. they are benign and can be safely ignored?)

3) Are they warnings that were just missed, and should be corrected in the example?

4) Other…?

To save you time, below are the actual WARNINGs seen...

array_mem_bottleneck
WARNING: [SCHED 204-69] Unable to schedule 'load' operation ('mem_load_1', array_mem_bottleneck.c:100) on array
'mem' due to limited memory ports. Please consider using a memory core with more ports or partitioning the array 'mem'. proj_array_mem_bottleneck:solution1 Jan 10, 2019, 12:36:13 PM

loop_imperfect
WARNING: [XFORM 203-542] Cannot flatten a loop nest 'LOOP_I' (loop_imperfect.c:99:34) in function 'loop_imperfect'
: the outer loop is not a perfect loop because there is nontrivial logic before entering the inner loop. proj_loop_imperfect:solution1 Jan 10, 2019, 1:44:39 PM

loop_max_bounds
WARNING: [RTGEN 206-101] Port 'loop_max_bounds/A_31' has no fanin or fanout and is left dangling.
Please use C simulation to confirm this function argument can be read from or written to. proj_loop_max_bounds:solution1 Jan 10, 2019, 1:47:26 PM

loop_pipeline
WARNING: [RTGEN 206-101] Register 'acc' is power-on initialization. proj_loop_pipeline:solution3 Jan 10, 2019, 1:52:28 PM
WARNING: [SCHED 204-69] Unable to schedule 'load' operation ('A_load_2', loop_pipeline.c:101) on array 'A' due to limited
memory ports. Please consider using a memory core with more ports or partitioning the array 'A'. proj_loop_pipeline:solution3 Jan 10, 2019, 1:52:25 PM

loop_sequential
WARNING: [XFORM 203-561] Updating loop upper bound from 32 to 31 for loop 'SUM_Y' (loop_sequential.c:106:1) in function
'loop_sequential'. proj_loop_sequential:solution1 Jan 10, 2019, 1:55:02 PM
WARNING: [XFORM 203-561] Updating loop upper bound from 32 to 31 for loop 'SUM_X' (loop_sequential.c:101:1) in function
'loop_sequential'. proj_loop_sequential:solution1 Jan 10, 2019, 1:55:02 PM

loop_var
WARNING: [XFORM 203-503] Cannot unroll loop 'LOOP_X' (loop_var.c:99) in function 'loop_var': cannot completely unroll
a loop with a variable trip count. proj_loop_var:solution1 Jan 10, 2019, 2:01:12 PM

pointer_arith
WARNING: [RTGEN 206-101] Register 'acc' is power-on initialization. proj_pointer_arith:solution1 Jan 10, 2019, 2:03:14 PM

pointer_array
WARNING: [XFORM 203-561] Updating loop lower bound from 10 to 11 for loop 'Loop-0' in function 'pointer_array'. proj_pointer_array:solution1 Jan 10, 2019, 2:05:27 PM
WARNING: [XFORM 203-561] Updating loop upper bound from 10 to 11 for loop 'Loop-0' in function 'pointer_array'. proj_pointer_array:solution1 Jan 10, 2019, 2:05:27 PM

pointer_basic
WARNING: [RTGEN 206-101] Register 'acc' is power-on initialization. proj_pointer_basic:solution2 Jan 10, 2019, 2:07:42 PM

pointer_cast_native
WARNING: [SYNCHK 200-23] pointer_cast_native.c:101: variable-indexed range selection may cause suboptimal QoR. proj_pointer_cast_native:solution1 Jan 10, 2019, 2:09:37 PM

pointer_double
WARNING: [SYN 201-107] Renaming port name 'pointer_double/pos' to 'pointer_double/pos_r' to avoid the conflict with
HDL keywords or other object names. proj_pointer_double:solution1 Jan 10, 2019, 2:12:01 PM

proj_pointer_multi (intended bad example?)
WARNING: [SYN 201-107] Renaming port name 'pointer_multi/pos' to 'pointer_multi/pos_r' to avoid the conflict with
HDL keywords or other object names. proj_pointer_multi:solution1 Jan 10, 2019, 2:14:42 PM
WARNING: [HLS 200-40] In file included from pointer_multi.c:1:
pointer_multi.c:100:9: warning: assigning to 'dout_t *' (aka 'int *') from 'const dout_t [8]' discards qualifiers [-Wincompatible-pointer-types]
ptr = a;
^ ~
pointer_multi.c:102:9: warning: assigning to 'dout_t *' (aka 'int *') from 'const dout_t [8]' discards qualifiers [-Wincompatible-pointer-types]
ptr = b;
^ ~
2 warnings generated. proj_pointer_multi:solution1 Jan 10, 2019, 2:14:41 PM

FIFO_port
WARNING: [SCA 200-202] Non-channel variable 'sc_FIFO_port_write_done' of module 'sc_FIFO_port' is used for inter-process
communications which may result in nondeterministic simulation behavior. Please consider changing it to an sc_signal. proj_sc_FIFO_port:solution1 Jan 10, 2019, 2:20:43 PM
WARNING: [XFORM 203-561] 'Loop-1' (sc_FIFO_port.cpp:105:18) in function 'sc_FIFO_port::Prc1' is an infinite loop. proj_sc_FIFO_port:solution1 Jan 10, 2019, 2:20:43 PM
WARNING: [XFORM 203-561] 'Loop-1' (sc_FIFO_port.cpp:126:18) in function 'sc_FIFO_port::Prc2' is an infinite loop. proj_sc_FIFO_port:solution1 Jan 10, 2019, 2:20:43 PM

types_composite
WARNING: [RTGEN 206-101] Port 'types_composite/frame_options' has no fanin or fanout and is left dangling.
Please use C simulation to confirm this function argument can be read from or written to. proj_types_composite:solution1 Jan 10, 2019, 2:26:00 PM
WARNING: [RTGEN 206-101] Port 'types_composite/frame_header_private_bits' has no fanin or fanout and is left dangling.
Please use C simulation to confirm this function argument can be read from or written to. proj_types_composite:solution1 Jan 10, 2019, 2:26:00 PM
WARNING: [RTGEN 206-101] Port 'types_composite/frame_header_crc_target' has no fanin or fanout and is left dangling.
Please use C simulation to confirm this function argument can be read from or written to. proj_types_composite:solution1 Jan 10, 2019, 2:26:00 PM
WARNING: [RTGEN 206-101] Port 'types_composite/frame_header_crc_check' has no fanin or fanout and is left dangling.
Please use C simulation to confirm this function argument can be read from or written to. proj_types_composite:solution1 Jan 10, 2019, 2:26:00 PM
WARNING: [RTGEN 206-101] Port 'types_composite/frame_header_samplerate' has no fanin or fanout and is left dangling.
Please use C simulation to confirm this function argument can be read from or written to. proj_types_composite:solution1 Jan 10, 2019, 2:26:00 PM
WARNING: [RTGEN 206-101] Port 'types_composite/frame_header_bitrate' has no fanin or fanout and is left dangling.
Please use C simulation to confirm this function argument can be read from or written to. proj_types_composite:solution1 Jan 10, 2019, 2:26:00 PM
WARNING: [RTGEN 206-101] Port 'types_composite/frame_header_emphasis' has no fanin or fanout and is left dangling.
Please use C simulation to confirm this function argument can be read from or written to. proj_types_composite:solution1 Jan 10, 2019, 2:26:00 PM
WARNING: [RTGEN 206-101] Port 'types_composite/frame_header_mode_extension' has no fanin or fanout and is left dangling.
Please use C simulation to confirm this function argument can be read from or written to. proj_types_composite:solution1 Jan 10, 2019, 2:26:00 PM

types_global
WARNING: [RTGEN 206-101] Global array 'Aout' will be exposed as RTL port. proj_types_global:solution1 Jan 10, 2019, 2:30:14 PM
WARNING: [RTGEN 206-101] Global array 'Aint' will be exposed as RTL port. proj_types_global:solution1 Jan 10, 2019, 2:30:14 PM
WARNING: [RTGEN 206-101] Global array 'Ain' will be exposed as RTL port. proj_types_global:solution1 Jan 10, 2019, 2:30:14 PM

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Xilinx Employee
Xilinx Employee
110 Views
Registered: ‎09-05-2018

Re: WARNING(s) in Xilinx HLS ‘Coding Style Examples’

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Hey @xilinxacct,

Some of those are purposeful, like the array for loop_imperfect. That example is meant to show an imperfect loop, and the warning complains that the loop is not perfect. I'm actually surprised types_global published a warning; the message seems purely informational.

In other cases, we might need to take a look at some of the examples and refresh them. But based on a quick look, most of the warnings don't adversely affect the specific coding style each example intends to demonstrate.

 

Nicholas Moellers

Xilinx Worldwide Technical Support
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Xilinx Employee
Xilinx Employee
111 Views
Registered: ‎09-05-2018

Re: WARNING(s) in Xilinx HLS ‘Coding Style Examples’

Jump to solution

Hey @xilinxacct,

Some of those are purposeful, like the array for loop_imperfect. That example is meant to show an imperfect loop, and the warning complains that the loop is not perfect. I'm actually surprised types_global published a warning; the message seems purely informational.

In other cases, we might need to take a look at some of the examples and refresh them. But based on a quick look, most of the warnings don't adversely affect the specific coding style each example intends to demonstrate.

 

Nicholas Moellers

Xilinx Worldwide Technical Support
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