We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Registered: ‎06-28-2008

What's the difference between ap_memory and bram ?

Hello, everybody.


As ug902 said,

"The bram interface mode is functional identical to the ap_memory interface.

The only difference is how the ports are implemented when the design is used

in Vivado IP Integrator:
•An ap_memory interface is displayed as multiple and separate ports.
•A bram interface is displayed as a single grouped port which can be connected

to a Xilinx block RAM using a single point-to-point connection."


However, I synthesized my code with  a sub function of matrix multiply.

With default ap_memory interface ,  the sub function could be optimized with

different latencies using configurations  such as "... ARCH = 3 ","..UNROLL_FACTOR = 4" and so on.

However, with bram directive , I found my code are NOT optimized for latency,

it always show the fixed latency.

What's the difference between ap_memory and bram ?


0 Kudos
1 Reply
Registered: ‎05-30-2018

Re: What's the difference between ap_memory and bram ?

Hi !

I know my answer is late, but I had the same question.


from page 68 in this doc:




I quote :


"bram — The same as ap_memory, except that when bundled using IP Integrator, the ports are not shown as individual ports, but grouped together into a single port."


They are referring to the Zynq book (page 321).


The reason why you're getting different results might be the number of r/w ports to that BRAM block.




0 Kudos