UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Explorer
Explorer
20,012 Views
Registered: ‎10-25-2012

When do I need to use HLS?

Jump to solution

I am a FPGA designer who is good at Verilog and VHDL. I am interested in learning to use Vivado HLS. 

 

But before I start, I think it is better to determine whether I need to learn it or not. I hope anyone has experience in Vivado HLS can discuss here like:

1. What kind of design you perfer to use HLS rather than HDL to do design?

2. What is your background? Like Software, hardware, RTL designer?

3. What is advantage that HLS over HDL ?

 

Thanks at advance. 

0 Kudos
1 Solution

Accepted Solutions
Teacher muzaffer
Teacher
30,730 Views
Registered: ‎03-31-2012

Re: When do I need to use HLS?

Jump to solution

I think the correct analogy is RTL is similar to a macro assembler and HLS is C/C++.

You should learn how to use HLS (assuming you know C/C++ already) if you find yourself designing simulation models in C/C++ while doing algorithm development and then converting them to RTL manually.

This mostly happens if you develop DSP (filters, video processing etc. ) code and you either design the algorithm yourself in C/C++ or are given the golden C/C++ model.

If your work mainly involves shuffling bits in/out and doing mostly control path work, HLS may not be that useful. If the starting point of your current work is not C/C++, HLS may not be useful.
If you prototype in C/C++, then convert to RTL then HLS is extremely useful. If you value your time and productivity HLS is useful.
If someone tells you that they can generate RTL manually better than any HLS tool (or you tell this to yourself), remember that we used to code in assembler, drew schematics for logic etc.

Ask yourself why no one does these anymore and remember there were a lot of people claimed they could write assembly code better than any compiler could generate code and interpolate the future of RTL from that.

- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
10 Replies
Explorer
Explorer
19,993 Views
Registered: ‎10-25-2012

Re: When do I need to use HLS?

Jump to solution
Anyone has idea?

Thanks.
0 Kudos
Xilinx Employee
Xilinx Employee
19,980 Views
Registered: ‎08-17-2011

Re: When do I need to use HLS?

Jump to solution

Hello,

 

I also would be interested to know what users have to say.

I'm guessing there is not one a simple answer (beside the obvious one being "go ahead and get into it").

 

Did you have a read of the main User Guide, Tutorial and/or Intro to FPGA using HLS documents (which ever you fancy - UG902, UG871 & UG998 respectively)?

 

One of the nice things is that you can easily do architecture exploration which, as an RTL designer, you probably will like. The promise of HLS over HDL are faster turnaround times for design, verification etc.. I'm not marketing guy, sorry :)

 

What kind of design do you have in mind?

What do you want to accelerate or what kind of IP do you want to design?

 

- Hervé

SIGNATURE:
* New Dedicated Vivado HLS forums* http://forums.xilinx.com/t5/High-Level-Synthesis-HLS/bd-p/hls
* Readme/Guidance* http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

* Please mark the Answer as "Accept as solution" if information provided is helpful.
* Give Kudos to a post which you think is helpful and reply oriented.
0 Kudos
Teacher muzaffer
Teacher
30,731 Views
Registered: ‎03-31-2012

Re: When do I need to use HLS?

Jump to solution

I think the correct analogy is RTL is similar to a macro assembler and HLS is C/C++.

You should learn how to use HLS (assuming you know C/C++ already) if you find yourself designing simulation models in C/C++ while doing algorithm development and then converting them to RTL manually.

This mostly happens if you develop DSP (filters, video processing etc. ) code and you either design the algorithm yourself in C/C++ or are given the golden C/C++ model.

If your work mainly involves shuffling bits in/out and doing mostly control path work, HLS may not be that useful. If the starting point of your current work is not C/C++, HLS may not be useful.
If you prototype in C/C++, then convert to RTL then HLS is extremely useful. If you value your time and productivity HLS is useful.
If someone tells you that they can generate RTL manually better than any HLS tool (or you tell this to yourself), remember that we used to code in assembler, drew schematics for logic etc.

Ask yourself why no one does these anymore and remember there were a lot of people claimed they could write assembly code better than any compiler could generate code and interpolate the future of RTL from that.

- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
Explorer
Explorer
19,965 Views
Registered: ‎10-25-2012

Re: When do I need to use HLS?

Jump to solution
Thanks very much, both of you.

OK, I think I got the point. If I do a lot of DSP design, need complex algorithm implmentation in FPGA, HLS is for me!

I think it is very deserve for me to learn the HLS. I know C/C++, I will enjoy HLS.

Thanks.
0 Kudos
Teacher muzaffer
Teacher
19,961 Views
Registered: ‎03-31-2012

Re: When do I need to use HLS?

Jump to solution
I will make this my signature: Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
0 Kudos
Scholar markcurry
Scholar
19,960 Views
Registered: ‎09-16-2009

Re: When do I need to use HLS?

Jump to solution

I was curious about the responses to this thread too. 

 

My opinion is HLS is a niche market right now.  I'm not convinced it'll move beyond that.

 

There's differences in the evolution of hardware design this time.  We've moved from SPICE to library cells and schematics, to some synthesis, to RTL design.  It's become easier at each stage by moving the level of abstraction up.  Each change has been evolutionary.  At each change there's a lot of overlap.  Designers could mix and match as neccesary, or use what they were comfortable with.  When synthesis was first getting traction there was a lot of debate about what parts of the designs should be "Synopsized". 

 

Which was all good.  You could use both.  A netlists still works, and is representable in verilog/VHDL.  The analogy to C/assembly still fits.  They mix well, and you can use both.

 

HLS, on the other hand approaches things from the other end.  Trying to evolve from the top down.  And it's like trying to fit a square peg in a round whole.  The whole notion of "think hardware" and the parallel nature of design is really gone in HLS - it's there, but as an ugly wart.  Every example HLS design I've seen has to have ugly pragmas, or other games that are necessary to represent the inherent '"parallelism" of hardware design.  Can you mix and match RTL with HLS - not easily at all.

 

I feel that there still plenty of room to evolve up.  Systemverilog moves up the abtraction level significantly with the use of higher level structures, arrays as first class citizens, and interfaces.  Xilinx is woefully behind in this support. 

 

Beyond that, clock-less transaction level modeling (still in Systemverilog) would be the next step.  6 years ago I needed to create a video scaler.  I first modeled it at the transaction level in Systemverilog.  This became my reference model for the RTL design.  I kept thinking at the time, wouldn't it be nice to have a tool that helped here. I think there's a company - Bluespec - that's persuing things like this - but I haven't kept up with the tech.

 

Anyway, it's interesting times.  Will see if my reticents leaves me as a dinosaur...

 

Regards,

 

Mark

 

0 Kudos
Explorer
Explorer
19,955 Views
Registered: ‎10-25-2012

Re: When do I need to use HLS?

Jump to solution
Hi muzaffer,

I didn't foget to do "Accept as solution". But I am expecting more discussion here.

Thanks.
0 Kudos
Teacher muzaffer
Teacher
19,951 Views
Registered: ‎03-31-2012

Re: When do I need to use HLS?

Jump to solution

SystemVerilog vs HLS: There are two issues with SystemVerilog it is a verification language and an implementation language and which parts are which is not clear (yet). I am pretty sure asynchronous TLM portion is not synthesizable. The synthesizable subset of SV is definitely fluid right now but I don't expect it cover the verification portions too much. BTW, Xilinx synthesizes SV nicely (I have used interfaces, structs, unions, packed arrays etc) but they are behind in simulation.
Also people don't do algorithm development in RTL (high level or not) languages. C/C++ is the main tool for this and something which synthesizes C/C++ (or at least a subset of it) is extremely welcome.
About mixing HLS with RTL: this is how it is used already. HLS can generate standard interfaces (apparently including AXI lite/stream which I haven't used so far) at your top level border and you can just add it to your top level RTL design. The reverse is also possible (ie using existing RTL blocks in HLS designs) but not supported.

There are several HLS tools (Catapult being one of the other main ones) which are getting a lot of use right now and ASIC/FPGA design methodology is defintely moving towards inclusion of HLS in the flow.

 

- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
0 Kudos
Explorer
Explorer
19,947 Views
Registered: ‎10-25-2012

Re: When do I need to use HLS?

Jump to solution
I have not do the algorithm development in industry. In university, we always use Matlab instead C/C++.
0 Kudos
Scholar markcurry
Scholar
7,399 Views
Registered: ‎09-16-2009

Re: When do I need to use HLS?

Jump to solution

@muzaffer wrote:
BTW, Xilinx synthesizes SV nicely (I have used interfaces, structs, unions, packed arrays etc) but they are behind in simulation.
.

Care to elaborate here?  I understand they've added Systemverilog support in Vivado - so only for Kintex7 and beyond.  (Which exludes me for quite a while).  From these forums it looks to me that the Systemverilog support is still very much in development (read buggy).

 

Yours is the first mention I've seen anywhere of any success. 

 

We've only been asking for the support for 6 years or so...

 


@muzaffer wrote:

Also people don't do algorithm development in RTL (high level or not) languages. C/C++ is the main tool for this and something which synthesizes C/C++ (or at least a subset of it) is extremely welcome.
.

I suppose this really my core argument.  We DO algorithm development in verilog, as I already mentioned.  And I argue that's it's more likely, and easier to pull the hardware person up a level of abstraction.  It's continuing the evolution as it has happened in the past..

 

This is opposed to pulling the software person down a level of abstraction.  Dealing wih all that yucky hardware stuff. :)  It's often hard to get the software person to "think hardware" (One of the most often used suggestions in these forums!)

But I agree the tool definetly has it's uses.

 

--Mark

 

0 Kudos