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Explorer
Explorer
1,196 Views
Registered: ‎08-26-2014

Why this HLS code is hanging?

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Hi guys,

 

I am having problems again with an HLS IP.

 

It is properly working inside HLS, even the co-simulation. But when I generate the IP and place it in a Vivado Block Design it hangs after the first execution.

 

Does anyone know why? Here the code:

 

void Conversion_to_float(const float a_G0, const float a_G1, const float a_G2, const float a_G3,
		const float a_G4, const float a_G5, const float b0, const float b1,	const float b2, const float b3,
		const float b4, const float b5, volatile unsigned int raw0, volatile unsigned int raw1, volatile unsigned int raw2,
		volatile unsigned int raw3, volatile unsigned int raw4, volatile unsigned int raw5, volatile float *DDR, volatile float *OCM)
{
#pragma HLS INTERFACE s_axilite depth=1 port=return
#pragma HLS INTERFACE m_axi depth=6 port=DDR offset=slave bundle=DDR_DATA
#pragma HLS INTERFACE m_axi depth=6 port=OCM offset=slave bundle=OCM_DATA

#pragma HLS LATENCY min=0 max=0
#pragma HLS INTERFACE ap_none depth=1 port=raw0
#pragma HLS INTERFACE ap_none depth=1 port=raw1
#pragma HLS INTERFACE ap_none depth=1 port=raw2
#pragma HLS INTERFACE ap_none depth=1 port=raw3
#pragma HLS INTERFACE ap_none depth=1 port=raw4
#pragma HLS INTERFACE ap_none depth=1 port=raw5

#pragma HLS INTERFACE s_axilite depth=1 port=b0
#pragma HLS INTERFACE s_axilite depth=1 port=b1
#pragma HLS INTERFACE s_axilite depth=1 port=b2
#pragma HLS INTERFACE s_axilite depth=1 port=b3
#pragma HLS INTERFACE s_axilite depth=1 port=b4
#pragma HLS INTERFACE s_axilite depth=1 port=b5
#pragma HLS RESOURCE variable=b0 core=FIFO_LUTRAM latency=0
#pragma HLS RESOURCE variable=b1 core=FIFO_LUTRAM latency=0
#pragma HLS RESOURCE variable=b2 core=FIFO_LUTRAM latency=0
#pragma HLS RESOURCE variable=b3 core=FIFO_LUTRAM latency=0
#pragma HLS RESOURCE variable=b4 core=FIFO_LUTRAM latency=0
#pragma HLS RESOURCE variable=b5 core=FIFO_LUTRAM latency=0
#pragma HLS INTERFACE s_axilite depth=1 port=a_G0
#pragma HLS INTERFACE s_axilite depth=1 port=a_G1
#pragma HLS INTERFACE s_axilite depth=1 port=a_G2
#pragma HLS INTERFACE s_axilite depth=1 port=a_G3
#pragma HLS INTERFACE s_axilite depth=1 port=a_G4
#pragma HLS INTERFACE s_axilite depth=1 port=a_G5
#pragma HLS RESOURCE variable=a_G0 core=FIFO_LUTRAM latency=0
#pragma HLS RESOURCE variable=a_G1 core=FIFO_LUTRAM latency=0
#pragma HLS RESOURCE variable=a_G2 core=FIFO_LUTRAM latency=0
#pragma HLS RESOURCE variable=a_G3 core=FIFO_LUTRAM latency=0
#pragma HLS RESOURCE variable=a_G4 core=FIFO_LUTRAM latency=0
#pragma HLS RESOURCE variable=a_G5 core=FIFO_LUTRAM latency=0

	*OCM = (float)raw0*a_G0+b0;
	*(OCM+1) = (float)raw1*a_G1+b1;
	*(OCM+2) = (float)raw2*a_G2+b2;
	*(OCM+3) = (float)raw3*a_G3+b3;
	*(OCM+4) = (float)raw4*a_G4+b4;
	*(OCM+5) = (float)raw5*a_G5+b5;

	*DDR = (float)raw0*a_G0+b0;
	*(DDR+1) = (float)raw1*a_G1+b1;
	*(DDR+2) = (float)raw2*a_G2+b2;
	*(DDR+3) = (float)raw3*a_G3+b3;
	*(DDR+4) = (float)raw4*a_G4+b4;
	*(DDR+5) = (float)raw5*a_G5+b5;
}

I am using Vivado HLS 2017.4, the MicroZed with the Zynq-7020, and 10ns period. I then connect the two output ports to the OCM through ACP, and to the DDR through HP. The error should be easy to reproduce.

 

It happened to me in another function. I found a temporary solution but here there is not much I can do.

 

Thanks for your help,

 

Cerilet

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1 Solution

Accepted Solutions
Explorer
Explorer
1,477 Views
Registered: ‎08-26-2014

Re: Why this HLS code is hanging?

Jump to solution

@hbucher, I know how to debug using an ILA. Actually, I use it quite often.

 

I finally managed to get the IP working. Like in the other post, it worked after changing the code to perform the same operations but writing it in another way. Here how the code looks like now:

 

float output[6];

output[0] = (float)raw0*a_G0+b0;
output[1] = (float)raw1*a_G1+b1;
output[2] = (float)raw2*a_G2+b2;
output[3] = (float)raw3*a_G3+b3;
output[4] = (float)raw4*a_G4+b4;
output[5] = (float)raw5*a_G5+b5;

*OCM = output[0];
*(OCM+1) = output[1];
*(OCM+2) = output[2];
*(OCM+3) = output[3];
*(OCM+4) = output[4];
*(OCM+5) = output[5];

*DDR = output[0];
*(DDR+1) = output[1];
*(DDR+2) = output[2];
*(DDR+3) = output[3];
*(DDR+4) = output[4];
*(DDR+5) = output[5];

After synthesis I saw it was using 30 DSP without improving latency at all. So I added this pragma as well:

 

#pragma HLS ALLOCATION instances=fmul limit=1 core

Believe it or not, now the IP performs well without modifying neither the block design nor the code.

 

I am still waiting someone from Xilinx to give me an answer why is this happening in this case and in the previous post.

 

In any case, thanks for your help @hbucher.

 

Best regards,

 

Cerilet

4 Replies
Scholar hbucher
Scholar
1,179 Views
Registered: ‎03-22-2016

Re: Why this HLS code is hanging?

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@cerilet 

What do you mean exactly by "hangs"? 

I assuming you are starting the component every time, correct?

Place an ILA on the DDR and OCM ports and trigger on a condition on the BRESP channel.

My hunch is that you are issuing an address on a port that does not support it. 

vitorian.com --- We do this for fun. Always give kudos. Accept as solution if your question was answered.
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Explorer
Explorer
1,148 Views
Registered: ‎08-26-2014

Re: Why this HLS code is hanging?

Jump to solution

Hi @hbucher,

 

thanks for your quick answer.

 

By hanging I mean that once I start the IP, idle and ready signals never go high.

 

I have tried with several memory regions, like OCM having low and high addresses, and DDR, but the behavior is the same.

 

Moreover, I have another IP with the similar task (making computations and writing results using two m_axi interfaces), and this one works well. So definitely is an HLS problem when implementing this specific IP.

 

It happened to me also in another IP that did not have an m_axi.

 

I'll check the BRESP right now.

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Scholar hbucher
Scholar
1,129 Views
Registered: ‎03-22-2016

Re: Why this HLS code is hanging?

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@cerilet You have to be comfortable with ILA debugging 

https://youtu.be/8mCafzPCWqs

vitorian.com --- We do this for fun. Always give kudos. Accept as solution if your question was answered.
I will not answer to personal messages - use the forums instead.
0 Kudos
Explorer
Explorer
1,478 Views
Registered: ‎08-26-2014

Re: Why this HLS code is hanging?

Jump to solution

@hbucher, I know how to debug using an ILA. Actually, I use it quite often.

 

I finally managed to get the IP working. Like in the other post, it worked after changing the code to perform the same operations but writing it in another way. Here how the code looks like now:

 

float output[6];

output[0] = (float)raw0*a_G0+b0;
output[1] = (float)raw1*a_G1+b1;
output[2] = (float)raw2*a_G2+b2;
output[3] = (float)raw3*a_G3+b3;
output[4] = (float)raw4*a_G4+b4;
output[5] = (float)raw5*a_G5+b5;

*OCM = output[0];
*(OCM+1) = output[1];
*(OCM+2) = output[2];
*(OCM+3) = output[3];
*(OCM+4) = output[4];
*(OCM+5) = output[5];

*DDR = output[0];
*(DDR+1) = output[1];
*(DDR+2) = output[2];
*(DDR+3) = output[3];
*(DDR+4) = output[4];
*(DDR+5) = output[5];

After synthesis I saw it was using 30 DSP without improving latency at all. So I added this pragma as well:

 

#pragma HLS ALLOCATION instances=fmul limit=1 core

Believe it or not, now the IP performs well without modifying neither the block design nor the code.

 

I am still waiting someone from Xilinx to give me an answer why is this happening in this case and in the previous post.

 

In any case, thanks for your help @hbucher.

 

Best regards,

 

Cerilet