04-21-2017 01:48 AM
I am trying to C/RTL co-simulate a module using Vivado Simulator (xsim) in Vivado HLS 2016.4. C simulation is passed, and synthesis completed without errors. But when co-simulated, it is stuck at ## run all. (When stopped forcefully it had generated a huge wcfg file of ~10GB).
1. What are the possible causes that simulation in running indefinitely at run all?
As per my understanding "run all" runs the simulation till all the transitions are completed. Is it stuck at some infinite loop or some kind?
2. How to debug the issue?
04-27-2017 03:26 AM
04-21-2017 02:15 AM
(1) This is a curious one. I've had a block that appears to do an infinite loop in cosim (ie runs for far more cycles than HLS claims it should, doesn't finish overnight) - but if I put it on an FPGA it works absolutely fine. This suggests a problem in the simulator rather than in the code itself. That's the first thing I'd try; do a hardware build with the block and see if it finishes.
(2) It's a really, really difficult one to debug. I never got around to it - I just went straight to the FPGA and tested it there. You can also try using a different version of HLS; my usual test suite is 2015.2 (tends to produce the smallest hardware), 2015.4 (fixes a few bugs in 2015.2), 2016.1 (more advanced AXI Masters), and 2016.4 (general improvements). Initial testing in 2017.1 is discouraging (ie blocks getting both larger and slower) but time will tell whether that's worthwhile.
04-21-2017 09:45 PM
1. Hardware is not available at this stage and it is not possible to try it out.
2. I tried in 2015.4 and it is behaving in the same way as 2016.4 (stuck at 'run all').
Does it have anything to do with the block level interface protocol (ap_ready, ap_start etc.)? The block is built with the default IO protocol, no directives used. The block takes an array as input, work on it and gives the output in an array. The input array is loaded with data by the test bench.
04-22-2017 11:34 PM
@apdmbn what constraints are you applying? First thing to try is to remove all constraints and try cosim and see if it passes. Then add your optimization constraints one by one to see which one is causing bad code to be generated. Usually dataflow has a problem where the fifos either become empty and never get filled again or they get full and they're never emptied which causes the infinite loop.
04-23-2017 07:48 PM
@muzaffer, no custom constraints are applied. Everything is synthesized with the HLS default directives. The arrays are implemented as memory. The input array is loaded from test bench, so it should not be empty.
04-27-2017 03:26 AM