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Visitor noahhuetter
Visitor
1,058 Views
Registered: ‎06-27-2017

axi stream simultaneous read and write operation

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I have an FSM design in HLS. In one state the block should send data from memory to axi stream and simultaneously read data from another stream to memory. The code looks something like that:

 

void controller_top(volatile uint8_t *memp, volatile uint32_t *cbus,
     AXI_STREAM &inData,
     AXI_STREAM &outData,
     ap_uint<1> rx_done)
{
#pragma HLS DATAFLOW

#pragma HLS INTERFACE m_axi depth=16 port=cbus offset=off
#pragma HLS INTERFACE m_axi depth=1168 port=memp offset=off bundle=memp
#pragma HLS INTERFACE axis register reverse port=inData
#pragma HLS INTERFACE axis register forward port=outData

#pragma HLS INLINE region

    static enum myState {S_INIT, S_IDLE, S_READ, S_STREAM, S_WRITE} state = S_IDLE;
    // Local memory for image data
    static uint8_t in_mem[IN_LINE_SIZE];
    static uint8_t out_mem[OUT_SIZE];
    // Data for mem to stream
    static bool runOut = false;
    // Data for stream to stream
    static bool runIn = false;

    switch(state)
    {
        case S_IDLE:
            //OPS
            state = S_READ;
            break;
        case S_READ:
            //OPS
            runOut = true;
            runIn = true;
            state = S_STREAM;
            break;
        case S_STREAM:
            /********* OUT *********/
            if(runOut)
            {
                outData.write(oPxl);
                // increment
                if (exit_cond)
                {
                    runOut = false;
                }
            }
            /********* IN *********/
            if(runIn)
            {
                if(!inData.empty())
                {
                    // store
                    iPxl = inData.read();
                    out_mem[sm_ctr++] = (uint8_t)iPxl.data;
                    // Exit condition
                    if (iPxl.last) runIn = false;
                }
            }
            /********* EXIT *********/
            if(!runOut && !runIn)
            {
                state = S_WRITE;
            }
            break;
        case S_WRITE:
            //OPS
            state = S_IDLE;
            break;
    }
}

In simulation it works:

Screenshot from 2018-06-01 14-57-33.png

 

BUT implemented on the FPGA, the TREADY signal from the incomming stream is never set high. My surrounding logic wants to send data to inData and asserts TVALID high but TREADY from the HLS core is always low. I can observe that the data is correct on the outData stream.

 

Any idea why this could be the case?

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1 Solution

Accepted Solutions
Explorer
Explorer
1,336 Views
Registered: ‎05-23-2011

Re: axi stream simultaneous read and write operation

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Hi Noah

I made something simmilar with two ingoing and two outgoing streams.
In your write state it would be better to check if the outgoing stream is full, because you use blocking accesses at the moment.
This can hang up up your state machine ( I made bad experiences with this).

I also didn´t use the while(1) loop. I used the auto restart feature of the HLS-IP.
Getting pipeline II=1 is realy hard because accessing the memory normaly takes two cycles.
Only if you access the memory sequencially you can get II=1, I think.

Kind regards

 

Thomas

5 Replies
Contributor
Contributor
1,049 Views
Registered: ‎04-18-2018

Re: axi stream simultaneous read and write operation

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Hi @noahhuetter,

I think it's due to the initialization time.

Try to put your switch into a while(1) and add the pipeline II=1 pragma inside.

-------------------------------------------------------------------------------------
Arthur DUMAS, FPGA Engineer, Consultant at ELSYS Design
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Visitor noahhuetter
Visitor
1,018 Views
Registered: ‎06-27-2017

Re: axi stream simultaneous read and write operation

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Thanks @arthur_dumas for the proposal. But when implementing the design in a while(1) loop the co-simulation doesn't even complete. Furthermore the application note XAPP1209 that describes a state machine also doesn't use a while loop.

 

Since the co-simulation works, why do you think it is due to some initialization time?

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Contributor
Contributor
1,010 Views
Registered: ‎04-18-2018

Re: axi stream simultaneous read and write operation

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Exact, I had never seen this XAPP. But they put the pipeline pragma instead of the dataflow one.
I ask you to do so because I've made a lot of image processing with HLS and I've never met this trouble and I thought it was due to the loop.
-------------------------------------------------------------------------------------
Arthur DUMAS, FPGA Engineer, Consultant at ELSYS Design
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Explorer
Explorer
1,337 Views
Registered: ‎05-23-2011

Re: axi stream simultaneous read and write operation

Jump to solution

Hi Noah

I made something simmilar with two ingoing and two outgoing streams.
In your write state it would be better to check if the outgoing stream is full, because you use blocking accesses at the moment.
This can hang up up your state machine ( I made bad experiences with this).

I also didn´t use the while(1) loop. I used the auto restart feature of the HLS-IP.
Getting pipeline II=1 is realy hard because accessing the memory normaly takes two cycles.
Only if you access the memory sequencially you can get II=1, I think.

Kind regards

 

Thomas

Visitor noahhuetter
Visitor
994 Views
Registered: ‎06-27-2017

Re: axi stream simultaneous read and write operation

Jump to solution

@thomasdon thank you so much! I was totally overseeing that issue. Of course the code blocks on write and doesn't reach the read part. 

 

Although I am still of the opinion that the synthesis tool should implement the two if statements (runOut/runIn) in parallel and then the blocking statement would have made no influence.

 

Anyway, inserting  

if(!outData.full())
{
}

fixed my issue.

 

Thanks again!

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