05-08-2017 05:29 AM
I am doing with Vivado HLS IP design, after synthesis design resource utilization shows BRAM is 99%.
I've vivado integrator design (without HLS IP Block) after bitstream generation resource utilization report is shows BRAM is 4%,
I added HLS IP into Vivado integrator design and i run the synthesis and generates the Bitstream.
i checked resource utilization report is shows BRAM is 36%.
how come suddenly the BRAM utilization Became 36% though HLS IP taking 99% BRAM.
I confused with this utilization report.
Is anyone what is the reason or any idea for the above subject, please give me valuable suggestions.
Thanks and Best Regards
01-15-2019 09:29 AM
If the 'part' you are targeting the same within HLS and Vivado?
Is there a 'unconnected' BRAM that is counted in HLS, and optimized out in Vivado?
Hope that helps
Please mark as solution accepted to close the issue. Kudos also welcomed :-)
01-19-2019 06:37 AM
Did you check the utilization after exporting the RTL as IP with synthesis, place and route options as these will give the exact utilization values whereas synthesis option in HLS converts the c/c++ language into HDL giving just utilization estimates but not the exact utilization.