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Observer chenj15
Observer
5,056 Views
Registered: ‎08-14-2016

dataflow on two functions with different II, is it possible?

The structure is like:

 

k = funcA(stream_in, X);
if(k==some_condition)
   funcB(X, stream_out);

func(A) is pipelined with II=1, it receive data from steam_in and put it into buffer X, and return a variable. 

 

whereas func(B) output is conditioned on the variable returned by funcA, when the condition is true, it will output some historical data from buffer X. There is a loop in funcB.

 

Is it possible to apply dataflow on these two function. 

 

I just want to write buffer out when some condition is met, without affect reading with II=1. 

 

Best,

Chongxi

 

 

 

 

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5 Replies
Scholar u4223374
Scholar
5,030 Views
Registered: ‎04-26-2015

Re: dataflow on two functions with different II, is it possible?

I can't see how dataflow would work there. You need the final output value from the first function (k) before starting the next one.

 

If it's possible to calculate "k" early in funcA, you could split that into another function (funcC), so the code looks like this:

 

k = funcC();
if (k == whatever) {
	funcA(streamIn,X);
	funcB(X, streamOut);
}

You can then apply dataflow inside the "if" statement. However, this only makes sense if funcC() can be run very fast.

Observer chenj15
Observer
5,021 Views
Registered: ‎08-14-2016

Re: dataflow on two functions with different II, is it possible?

Thank you very much for replying that! 

 

In my case, however, k is dependent on data stream-in. Say you build a FSM in funcA with II, it receive axi-stream data every clock, and when it received a last signal, funcB execute and funcB output k buffered data. 

 

I don't know how to make the funcB not to dependent on funcA, when it receive a last signal, it should start output and without affecting receiving stream data with II.

 

I think this is a universal pattern in design, there got to be some way in HLS but I could not find it. I appreciate it if you could give me a hint. Thanks! 

 

Best,

Chongxi

 

 

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Scholar u4223374
Scholar
4,984 Views
Registered: ‎04-26-2015

Re: dataflow on two functions with different II, is it possible?

Hmm, that's potentially tricky. To be honest, I haven't had a whole lot of luck with the DATAFLOW pragma; I've got a few designs using it but mostly I end up doing function-level pipelining by hand. This would result in code something like the following:

 

int X[1024];
int Y[1024];
bool k = 0;
for (int i = 0; i < 1000; i++) {
	bool k_old = k;
	if (i & 0x01) {
		k = funcA(stream_in, X);
		funcB(Y,stream_out,k_old);
	} else {
		k = funcA(stream_in, Y);
		funcB(X,stream_out,k_old);
	}
}

void funcB(int Z[1024], hls::stream<int> stream_out, bool enable) {
	if (!enable) {
		return;
	}
	
	// function continues...
}

An explanation: you've got two buffers, X and Y. One is always being filled while the other is being emptied. Within the loop, funcA and funcB run simultaneously, which will mean that funcA never has to wait provided that funcB runs in less time than funcA (obviously if funcB blocks for a long time then the buffers will fill up and funcA will be blocked; no way around that).

 

You'll notice that I've moved the check for whether funcB should run inside funcB. If you enclose funcB in an "if" statement then HLS will not be able to run funcA and funcB in parallel, even if they're totally independent (as they are in this case). The solution is to have funcB run every time, but just return without doing anything if "k" is not asserted.

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Observer chenj15
Observer
4,878 Views
Registered: ‎08-14-2016

Re: dataflow on two functions with different II, is it possible?

Thanks! Have you tried it? I will post the result when I am able to try this way. Currently I just delete all the pragma and try not to finish the task in II=1. 

 

 

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Scholar u4223374
Scholar
4,866 Views
Registered: ‎04-26-2015

Re: dataflow on two functions with different II, is it possible?

I haven't tried in your specific case (because I don't know what goes into your funcA and funcB), but I've used this basic layout for 10+ of my own modules. Never had an issue with it, apart from HLS insisting that each of the buffers has to be in its own RAM (in HDL code there are more efficient methods available).

 

 

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