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219 Views
Registered: ‎05-12-2018

different utilization report between systhesis and export RTL

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Hi all,

I have a question about ultilization report between systhesis and export RTL.

In the export RTL, It uses additional SRL & SLICE and orther values is different synthesis report.

Could you please explain it for me?

Thank you,

Quan Nguyen

The report is as bellow:

################Synthesis#############

* Summary:
+-----------------+---------+-------+-------+-------+
| Name | BRAM_18K| DSP48E| FF | LUT |
+-----------------+---------+-------+-------+-------+
|DSP | -| -| -| -|
|Expression | -| -| -| -|
|FIFO | 3| -| 152| 423|
|Instance | 5| 33| 7567| 11694|
|Memory | -| -| -| -|
|Multiplexer | -| -| -| 11|
|Register | -| -| 7| -|
+-----------------+---------+-------+-------+-------+
|Total | 8| 33| 7726| 12128|
+-----------------+---------+-------+-------+-------+
|Available | 120| 80| 35200| 17600|
+-----------------+---------+-------+-------+-------+
|Utilization (%) | 6| 41| 21| 68|
+-----------------+---------+-------+-------+-------+

################################################

#####Export RTL#####

#=== Resource usage ===
SLICE: 2279
LUT: 6534
FF: 7199
DSP: 33
BRAM: 8
SRL: 508

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Contributor
Contributor
184 Views
Registered: ‎03-13-2017

Re: different utilization report between systhesis and export RTL

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The synthesis report is just a roughly estimation, you have to export the design and at least synthesize it to get a reliable utilization, which also depends on other factors releted to the full design like FPGA occupation and congestion.
The synthesis report also depends by the tooling release, see posts 1 2



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Contributor
Contributor
185 Views
Registered: ‎03-13-2017

Re: different utilization report between systhesis and export RTL

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The synthesis report is just a roughly estimation, you have to export the design and at least synthesize it to get a reliable utilization, which also depends on other factors releted to the full design like FPGA occupation and congestion.
The synthesis report also depends by the tooling release, see posts 1 2



Moderator
Moderator
153 Views
Registered: ‎05-31-2017

Re: different utilization report between systhesis and export RTL

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HI @hongquan18196,

As correctly indicated by @baltamthe utilization after exporting the RTL as IP with synthesis, place and route options will give the exact utilization values whereas synthesis option in HLS converts the c/c++ language into HDL giving just utilization estimates but not the exact utilization.

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