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Cannot set generic/parameter within IP

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Adventurer
Posts: 50
Registered: ‎11-26-2016
Accepted Solution

Cannot set generic/parameter within IP

[ Edited ]

Hi,

 

The UltraScale Devices Gen3 Integrated Block for PCI, which I use in tandem PCIe Configuration, contains a parameter MCAP_FPGA_BITSTREAM_VERSION. This can be used as a user defined register to identify the bitstream that is currently loaded in Stage 1 already.

https://www.xilinx.com/Attachment/Xilinx_Answer_64761_Ultrascale_Devices_v8.pdf, Table 8

 

However, how can I set the parameter?

 

The usual way using the Synthesis Options does not work for me, since the parameter is not in the top level of the design i guess:

 

"-generic MCAP_FPGA_BITSTREAM_VERSION=32'hdeadbeef"

this does not work either:

 

set_property generic {MCAP_FPGA_BITSTREAM_VERSION=32'hdeadbeef} [current_fileset]

 

Edit: For verification I actually built the design and tested it on HW, since I was not sure if the changes will be reflected in the sources.


Accepted Solutions
Adventurer
Posts: 50
Registered: ‎11-26-2016

Re: Cannot set generic/parameter within IP

According to Xilinx Support this is a issue that will be fixed in the next Vivado Release.

Currently the only option is to edit the IP sources by hand. After that IP re-generation, altering Settings, ... is not allowed any more.
In order to pass the parameter the OOC run must be disabled (setting to Global).

View solution in original post


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Moderator
Posts: 953
Registered: ‎09-15-2016

Re: Cannot set generic/parameter within IP

Hi @so-lli1

 

Do you have access to the IP source code? if yes, you can try modifying or setting the parameter in the IP file itself. Refer this link:

https://www.xilinx.com/support/answers/57546.html

 

Also just FYI the parameters won't pass from top to bottom hierarchy as long as they are not declared in the top. Setting the parameter through general settings or synthesis settings won't work in that case.

 

Regards

Rohit

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Regards
Rohit
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Adventurer
Posts: 50
Registered: ‎11-26-2016

Re: Cannot set generic/parameter within IP

First of all, thank you for your quick response @thakurr.

 

The parameters have to be adjusted automatically (in a script), changing the source code won't work well for me.
Its the PCIe Core, I dont really like the idea to switch it to "managed", since any changes in the future will be hard (i think).
Is ist possible to redirect the parameter to the top level if I set the IP to "managed"? (it is part of a Block Design)

I thought so, because we use this method regularly, but usually all the generics are in the top level.

 

 

 

 

Moderator
Posts: 953
Registered: ‎09-15-2016

Re: Cannot set generic/parameter within IP

Hi @so-lli1

 

>>Is ist possible to redirect the parameter to the top level if I set the IP to "managed"? (it is part of a Block Design)

Can you try last section i.e IP instance in an IPI of the above link given earlier. This is the only way i can see to set the parameter of IP.

Also check the below discussion where it say you cannot pass generic from top to IP because by default IPs are synthesized as OOC,hence by the time the IP see the generic it is already a netlist - the functionality of the netlist can't be changed at this point. 

https://forums.xilinx.com/t5/Vivado-TCL-Community/Get-generic-value-from-Tcl/td-p/780458

 

Regards

Rohit

Regards
Rohit
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
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Adventurer
Posts: 50
Registered: ‎11-26-2016

Re: Cannot set generic/parameter within IP

According to Xilinx Support this is a issue that will be fixed in the next Vivado Release.

Currently the only option is to edit the IP sources by hand. After that IP re-generation, altering Settings, ... is not allowed any more.
In order to pass the parameter the OOC run must be disabled (setting to Global).