02-20-2019 09:12 AM
How can I collect a list of the VHDL generics (or Verilog parameters) of a VHDL entity (or Verilog module) from Tcl?
I am hoping to obtain a comprehensive list my top module's generics/parameters along with their values. Ideally this would even include generics/parameters that were not explicitly set by the user and instead just use their default values.
I know this must be possible since "write_vhdl" collects all VHDL generics of the top module and writes them as "attributes" in a VHDL netlist. For example, after elaboration of the following entity:
entity test is generic ( G_GENERIC : natural := 1 ); port ( clk : IN std_logic; ... ); end test;
"write_vhdl" will result in the following:
entity test is port ( clk : IN std_logic; ... ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of test : entity is true; attribute G_GENERIC : integer; attribute G_GENERIC of test : entity is 1; ... end test;
So, somehow "write_vhdl" is able to determine the list of VHDL generics and write them to this VHDL netlist as attributes.
Any advice regarding how I can obtain this information via Tcl is much appreciated.
As a side note, is the source code for Vivado utilities like "write_vhdl" available somewhere? If I could see the "write_vhdl" source, I might be able to figure this out. I could not find this procedure's definition in my Vivado installation.
02-23-2019 08:10 AM - edited 03-03-2019 10:34 PM
A similar query has been discussed in following forums post:-
Have a look at it, let me know if it resolves your query.
02-25-2019 09:35 AM
Thank you for your response @chinmays! Unfortunately, that link (was broken, fixed here: https://forums.xilinx.com/t5/Vivado-TCL-Community/Get-generic-value-from-Tcl/td-p/780458) does not resolve my query for a few reasons:
This method does seem to give the values for all generics (even those which use default values and area not explicitly set).