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Participant
Participant
32,347 Views
Registered: ‎08-23-2012

Connecting signals to ground in Vivado block design

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I'm replicating a ISE tutorial design to Vivado. In that tutorial, some of the IP input signals are tied to "net_vcc" or "net_gnd" It's not clear how I would accomplish this in the Vivado Block Design IP integrator.

 

Any suggestions?

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Xilinx Employee
Xilinx Employee
49,162 Views
Registered: ‎08-02-2011
You don't assign it anything. The IP (may or may not) have pin tie off values already defined. There should be little 1's and 0's around the ports if they are defined (look at the resets or something).

If they aren't defined or you want to change the values, you must use a 'constant' block
www.xilinx.com

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Xilinx Employee
Xilinx Employee
32,343 Views
Registered: ‎08-02-2011

Two things
1) There are default tieoffs on ports (use the filters to enable them so you can see their values). Be careful with default tieoffs if you are building a hierarchical design.
2) Use a 'Constant' block

www.xilinx.com
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Participant
Participant
32,336 Views
Registered: ‎08-23-2012

How do I "use the filters"? Is this something I set in Vivado? I can't find any features in Vivado with the term "filter" in it.

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Xilinx Employee
Xilinx Employee
32,334 Views
Registered: ‎08-02-2011

Sorry, I forgot what it was called ha!

 

bd_opts.png

www.xilinx.com
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Participant
Participant
32,332 Views
Registered: ‎08-23-2012

Okay, I already had that open and all the boxes are checked. However, it's still not clear how to assign the default. I right click in the block design panel and Create Port...

 

In the popup, I give it a name, set the direction to input, and type to "other", but there is no default field, so I'm still missing something.

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Xilinx Employee
Xilinx Employee
49,163 Views
Registered: ‎08-02-2011
You don't assign it anything. The IP (may or may not) have pin tie off values already defined. There should be little 1's and 0's around the ports if they are defined (look at the resets or something).

If they aren't defined or you want to change the values, you must use a 'constant' block
www.xilinx.com

View solution in original post

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Participant
Participant
32,327 Views
Registered: ‎08-23-2012
Okay, that's the detail I was missing. No little 1's or 0's, so i'll use the constant block.

Thanks.
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Newbie
Newbie
31,904 Views
Registered: ‎12-16-2013

Hi,

 

How can I split the data_in_to_device[10:0] vector to individual signals

 

for example

data_in_to_device(0) ---> to input

data_in_to_device(1) ---> to input

data_in_to_device(2) ---> to input

 

 

 Screenshot from 2013-09-16 20:55:13.png

 

 

 

 

or is there an IP which performs the opposite of concat IP

 

 

 

Thanks!!

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Xilinx Employee
Xilinx Employee
31,901 Views
Registered: ‎08-02-2011
Yes, the 'Slice' block
www.xilinx.com
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Visitor
Visitor
31,325 Views
Registered: ‎03-23-2014

Constant block is EXTREMLEY obfuscating - there is no way to name it like GND  or VCC.

How I can mark it someway to see, which value is set on it?

what.png
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Xilinx Employee
Xilinx Employee
17,398 Views
Registered: ‎08-02-2011
You can re-name the block in the 'properties' window
www.xilinx.com
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Visitor
Visitor
17,223 Views
Registered: ‎03-23-2014

Thank you, it is realy helped.
But would be great to use some simpler way to connect pins to GND/VCC like another menu option near "Disconnect Pin"

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Visitor
Visitor
16,763 Views
Registered: ‎06-04-2013

Hi,

Have you solved the problem you mentioned?

Iif yes how?

Actually I want to split my 64 bit signal to two 32 bit signals but could not find any slice block to do that.  A 64 bit input is coming from outside world.

Thanks in advance.

/Babar

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Xilinx Employee
Xilinx Employee
16,746 Views
Registered: ‎02-06-2013

Hi

 

You can try as shown in the snapshot belowslice.png

Regards,

Satish

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