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bent93
Participant
Participant
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Registered: ‎10-17-2018

Decrease number of calls to get_net_delays to improve script runtime

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Hi,
I am working with get_net_delays to extract delays from my design. To do that, I need thousands of calls to get_net_delays which slows my script down drastically.

 

get_net_delays -of_objects [get_nets mynet]

returns the delay objects for all pins the net is connected to. I noticed that it takes around the same time as checking the delay for a single sink pin:

 

 

get_net_delays -of_objects [get_nets mynet] -to [get_pins myinpin]

 

This tells me that querying the delay once per net and then iterating over the result is much faster than iterating over the pins and calling get_net_delays for each of them. I implemented that and my script got much faster.

Now, is there a way to do the same with nets too? Can I query the delays for a bunch of nets instead of a single one? I expect get_net_delays to check some kind of database to get the delays, so this could decrease the runtime even further.

It seems like this was possible in earlier versions of Vivado because the TCL commands reference guide for version 2013.4 has the following hint in the description of the -of_objects parameter of get_net_delays on page 487:

 

Tip Use -of_objects [get_nets*] to return the delays for all nets in the design

The hint was removed at some point. I don't know when but  it is gone in the guide for version 2019.2 and I get the following error:

get_net_delays -of_objects [get_nets *]
ERROR: [Common 17-56] 'When used with -to <objects>, -of_object <net>' expects exactly one object got '16'.

The error message suggests I used to -to option, but as you can see I did not. Nevertheless the command fails.

Is there a workaround to continue doing this? Back when it was possible, did it run faster than querying the nets individually?

 

 

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rshekhaw
Xilinx Employee
Xilinx Employee
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Registered: ‎05-22-2018
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rshekhaw
Xilinx Employee
Xilinx Employee
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Registered: ‎05-22-2018
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bent93
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Registered: ‎10-17-2018

Thanks, the problem discussed is very similar indeed, but the result is not going any further than what I elaborated on above, right?

What I take from that is: no, there is no way of getting all the delays at once and then working with the result, I need to call get_net_delays for each net. Is that correct?

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bent93
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Registered: ‎10-17-2018

@rshekhawcan you confirm?

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rshekhaw
Xilinx Employee
Xilinx Employee
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Registered: ‎05-22-2018

Hi @bent93 ,

Yes, as per my understanding that is the way it is.

Thanks,

Raj

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bent93
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Registered: ‎10-17-2018

Thank you @rshekhaw.

Nevertheless, I wonder how Vivado can route complete designs with correct timing when the calculation of timings alone takes that much time. My design is relatively small and routing (takes around 2 minutes) is much much faster than extracting all the delays (about 25 minutes).

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