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trueliving
Visitor
Visitor
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Registered: ‎04-10-2021

During presence of block design Version control with vivado is giving a different bit files

Hi,

I am using vivado 2019.2 and zcu111 board.

I have a project compiled on zcu111.where i have generated a tcl script and sourced the block design in the tcl script. I could able to generate and compile a new project using tcl script. But when i have compared the bit file of both original project and  tcl generated project. It is different .

I could see all parameter in original project and tcl generate project have same values and interfaces in the block design. But there was naming difference in compilation , original project was taking clk_wiz_0_1_synth_1 and tcl generated project was taking clk_wiz_0_0_synth_1.

To eliminate this difference i have generated the block design from the scratch  even then the bit files differs.

"Threads", "OS" and "vivado version" is same.

when the same procedure is repeated for a project "without block design" it was giving same bit files.

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amaccre
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Moderator
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Registered: ‎04-24-2013

HI @trueliving ,

I am not clear on your question, but if you are having issues with repeatability when all the input files are the same then have a look at Answer Record 61599

https://www.xilinx.com/support/answers/61599.html

Setting the maxThreads to 1 is important, you can also turn on checksum outputs for synthesis with the following command:

set_param netlist.allowChecksum true

If the input files are functionally equivalent but not identical then the output results can differ but be equivalent.

Are you having functional differences or is it only the bitstream is not identical after each run?

Best Regards
Aidan

 

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trueliving
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Registered: ‎04-10-2021

Hi @amaccre,

Thanks for responding the post.

I was generating a project using tcl script in vivado 2019.2 . By following these steps  file -> project -> write tcl -> copy sources to new project. And then sourcing the block design.tcl file in that  project.

when comparing the original project with tcl generated project . I could observe all the source files and block design IP's  are exactly same. It is only the bitstream which is not identical.

Even I have tried with your suggestion by Setting the maxThreads to 1 and set_param netlist.allowChecksum true. which is not giving the same bit stream file 

when the same procedure is repeated for  another project "without block design" it was giving same bit files.

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trueliving
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Visitor
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Registered: ‎04-10-2021

Hi @amaccre

Do you have any other suggestions. which can solve my issue.

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amaccre
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Registered: ‎04-24-2013

Hi @trueliving ,

Other than the bitstreams not being identical, what issues are you seeing? It is possible for the runs not to produce identical results and still be functionally equivalent.

If there is a date / time stamp in any of the IP then this will be different each time that you regenerate it. If there are multiple copies of the same IP used in the Block Design then the instance 1 may be generated the first time it is run and instance 2 the second time. Other than the names there will be no difference between them but this is enough to produce a difference in the results.

When you looked at the checksum values, at which point did you see the difference in the runs, this should indicate when the divergence started?

When you recreate the block design, write out the block design tcl file again and compare the two versions. Is there any difference to any of the settings?

If you need to guarantee that you are using exactly the same bitstream then the easiest way to do so is to add it to your project backup

Unless the resulting bitstream is incorrect then this is not an issue with the tools as there are many reasons why it may not be identical but equivalent.

Best Regards
Aidan

 

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trueliving
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Registered: ‎04-10-2021

Hi @amaccre,

functionally wise it is giving the same result.

In my block design I have multiple copies of same ip used. 

I have checked the log files in the runs folder. what i observed in the block design is  zynq Ultrascale + RF Data Converter, Axi BRAM controller and Block memory generator is giving me different checksum even though all parameters are exactly same for both the projects. What might be the reason for these?

I have recreate the block design, written the block design tcl file again and compared the two versions. It is giving the same setting. And even producing the same bit files.

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trueliving
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Registered: ‎04-10-2021

Hi  @amaccre,

Do I need to try anything else to get same bitstream.

 

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amaccre
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Moderator
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Registered: ‎04-24-2013

Hi @trueliving ,

Depending on your IP it may not be possible to guarantee that the bitstream will be identical every time, if the checksums are not then it won't be.
If there is no functional problem then why is this an issue? If you have to guarantee that you program the device with an identical bitstream every time then the simplest solution is to back up the bitstream along with your project.

Alternatively you can save the generated output products for each IP run so they are not generated again. This way their results and checksums won't have changed between bitstream generations.

Best Regards
Aidan

 

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