Generate Memory Initialization files for IP

[tud_hartmann]

Hello,

I try to integrate Xilinx IP flow into our local design flow (in non-project mode). I managed to create the IP (xci, dcp, simulation sources) from TCL script. However, for simulation sources generate_target does not create memory initialization files (*.mem). I tried to execute generate_mem_files after generate_target {simulation} [get_ips <ipname>], but I only get:

WARNING: [Memdata 28-80] Empty top found while merging BMM files!
WARNING: [Memdata 28-176] There are no bmm files or elf files. Therefore Vivado could not produce any .mem files. Check the design for the existence of processors and associated elf files.

What is the correct way to get those files? I'm trying this with Vivado 2016.4 and MIG DDR4 v2.1.

Thanks and best regards,

Stephan

[thakurr]

Hi @tud_hartmann

As the warning says there are no bmm or elf files in the design. Please follow the steps mentioned in the below link of AR and then run the tcl command generate_mem_files:

https://www.xilinx.com/support/answers/59568.html

Hope this helps.

Regards

Rohit

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[tud_hartmann]

Hi @thakurr,

the IP (in-memory) project has an BMM file and three ELF files, created as follows:

create_project -in_memory -part xcvu095-ffva2104-2-e
create_ip -name {ddr4} \
          -version {2.1} \
          -vendor {xilinx.com} \
          -library {ip} \
          -module_name {ddr4_0}

# set ip properties via set_property ...
generate_target {simulation} [get_ips ddr4_0]

The scoped refs and scoped cells of the BMM and ELF files look correct. If I set the toplevel module:

set_property top {ddr4_0} [current_fileset]

then generate_mem_files does not produce any warning, but also doesn't generate any mem file.

Best Regards,

Stephan

[thakurr]

Hi @tud_hartmann

Can you please verify that BRAM was intialized once implementation is done? Refer the step 5 of AR#59568.

Regards

Rohit

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[vemulad]

Hi @tud_hartmann

Are you using link_design command in your script file?

Can you try specifying the top module name in this command like below?

link_design –top ddr_top –part <fpga_part_name>

[tud_hartmann]

Hi @vemulad, @thakurr

implementation of the toplevel runs without any problems. I just need the memory initialization files for simulation of the IP (IES and ModelSim/Questa).

Best Regards,

Stephan

[shareef@phoelex.com]

Did you ever solve this?  It seems like the bug/issue still hasn't been fixed.