10-21-2015 01:03 PM
It appears to be rather cumbersom to update the tools SDK and Vivado. I created projects under 2015.2 and now want to use 2015.3. The directories and other environment issues make this not as straight forward as it should be.
Does anyone know of any tricks or scripts to automate the process?
10-28-2015 11:22 AM
Using TCL based scripts to create Vivado project and to build design is one way to have Xilinx tools switching smoother. First time I saw such approach was in Ettus USRP SDR project where tcl scripts were used to create (ISE 12.x) project files.
I use Vivado TCL script mode to create all outputs for Zynq projects (.bit, FSBL and device-tree). In very short description, TCL script collects project sources (all my source files are under version control): HDL sources (*.v), IP (*.xci) and constrain (*.xdc) files, it loads Block Design tcl (it is Zynq based project, Block Design can be exported to tcl file from Vivado), sets project options, etc. It creates Vivado project file (.xpr) which I can open with Vivado IDE or start synth and impl build in tcl. This way allows me to have in version control only real source files, everything else is re-generated by (newer) Xilinx tools.
Build (synth and impl) can also be started in tcl script so this approach is also usable for Continuous Integration Tool builds. From tcl script it is also possible to export HW and build FSBL and device tree. This are inputs to next build steps to produce bootable Zynq image (U-Boot, Linux kernel and Linux OS file system). But this is different ARM cross-compile task, that does not depends on switching Xilinx tools (older or different ARM cross-compilers are ok too).
Recently I switched from Vivado 2015.1 to Vivado 2015.3. I have first set the tools environment to Vivado 2015.3 (..../Xilinx/Vivado/2015.3/settings64.sh) and then start Vivado in tcl mode with my script as input. I got new Vivado 2015.3 .xpr file that I open in IDE. What I need to do next was to confirm IP upgrades, e.g. FIFO IP was new version, after confirm upgrade I got new .xci to commit in version control. After that I started build from Vivado IDE to check that design builds OK.
TCL script builds FSBL and device tree too. Xilinx tools switching is transparent for FSBL. For building device tree I picked new device tree definitions tagged with xilinx-v2015.3 from Xilinx GIT (https://github.com/Xilinx/device-tree-xlnx). This files are then source to device-tree tcl script building to produce .dts .dtsi files (link in siktap reply).
That was all I did to switch from 2015.1 to 2015.3. After that I can start complete build (.bit, FSBL and device-tree) in Vivado TCL mode from fresh version control check-out, any time I need.
The TCL script I use is not "one liner" but it is also not so complicated to create. For the very first time you must start with Vivado IDE. Once you build OK with IDE, you just need to find the right Vivado tcl commands to do the same things in tcl script.