Get generic value from Tcl

[geschema1]

Hi,

how can I get the values of my design's top-level generics from Tcl?

I've tried using "get_property generic" but it returns only the generics that have been explicitely set in the project settings.

Thanks,

Guy.

[pratham]

@geschema1 A way here

https://forums.xilinx.com/t5/Vivado-TCL-Community/Using-Tcl-to-set-a-verilog-hard-coded-value-pre-synthesis/td-p/654116

[geschema1]

Hi @pratham, thanks but what I'm looking for is a way of getting the values of my top-level generics.

[pratham]

If you use the method discussed in the thread you could read it using get_property. If you are looking for a way without having to use that method then I don't know a way.

[geschema1]

"get_property generics" only returns the generics that have been explicitely set in the project settings. The ones that use the default values specified in the RTL code do not show up in the list that is returned by get_property.

[pratham]

@geschema1 Did you read a thread referred above?  I am talking about using get_property with the method discussed in the thread, not get_property generics, I am well aware of that.

[avrumw]

So, if I understand correctly, you have a generic defined at the top level of your RTL and given a value in the RTL code, and you want to access the value of this generic in Tcl.

This is tricky...

First, realize that nothing like this can be done until at least after elaboration (Open Elaborated Design in project mode, or synth_design -rtl in non-project mode). Any point after this (i.e. after synthesis) will also work.

When a cell is instantiated, any parameter/generic of the cell will become a property of that cell. So, it is possible to get the generic of an instantiated sub-module of the design. Let's say you have a sub-module named "my_mod", which is instantiated at the top level design as instance "my_mod_i0" and inside that there is a generic named "my_generic". In this case, you can get the value by

get_property my_generic [get_cells my_mod_i0]

However, I can't find a way of getting this from the "top" instance - there is no equivalent to "get_cells my_mod_i0" that returns the top level instance. So, if the generic you need propagates down to a submodule, you can get it there. Even if it doesn't, you can pass it into any sub-module in your RTL (even if it doesn't use it), just so that the command above works.

The only other option is to search for it in the RTL. Tcl can open files and has regular expression search capabilities, so you can do text searches to find the definition of the generic in the top level RTL file (as text). 

Avrum

[geschema1]

@pratham could you please post an example of how you would read all top-level generics from Tcl? I'm sure other people who will come across this thread in the future will appreciate that too.

Thanks,

Guy.

[geschema1]

Hi @avrumw, this sounds good in theory as the generic is question is propagated down a few levels of hierarchy. But command "get_property AuroraType_g [get_cells {i_foif_top/i_aurora}]" unfortunately returns an empty list. Also, I don't see any generics in the Vivado "Cell Properties" view. Please note that I'm using Vivado 2015.4 for this project.

[avrumw]

If the cell you are using is an instantiation of an IP (which it probably is since I see the word "Aurora"), this may be more complicated.

IP's are synthesized out of context, and are only merged with the rest of the design before the implementation phase begins. So, if you are doing this with a synthesized design, then it is possible the cell is still a black box, and hence won't contain the generic.

That being said, you cannot pass a generic into an IP - pretty much for the same reason - the IP is synthesized OOC, and hence by the time the IP sees the generic it is already a netlist - the functionality of the netlist can't be changed at this point. But, the tools complain (critical warning) if you try and instantiate an IP with a generic (at least they do in later versions, and I am only certain about Verilog, not VHDL) - so if the aurora really is an IP you shouldn't be able to pass generics into it...

Try it on a non-IP module. I know that it can be done in Verilog on an RTL cell (I tried it before posting the solution).

Avrum

[geschema1]

@avrumw, the target cell is not an IP. It's a VHDL component. It is possible that the technique you decribed works only with Verilog?

[avrumw · Accepted solution]

Nope - I just tried it in VHDL, and it works...

At the top level, of the design (this is the wave_gen example design - you may be able to open it from the example designs), I have a generic defined

entity wave_gen is
    Generic (CLOCK_RATE_RX : integer := 200_000_000;
             CLOCK_RATE_TX : integer := 193_750_000;
             PW            : integer :=          3;
             BAUD_RATE     : integer :=    115_200;
             LED_USE       : string  :=     "TXDR"     -- other choice is "RXFB"
           );
    Port (  
...

The BAUD_RATE generic is passed into the instance uart_rx_i0

       uart_rx_i0: uart_rx 
          generic map (
                   BAUD_RATE      =>  BAUD_RATE,    
                   CLOCK_RATE     => CLOCK_RATE_RX           
                )
           port map (rst_clk_rx   => rst_clk_rx,                      -- active high, managed synchronously
                     clk_rx       => clk_rx,                          -- operational clock
                     rxd_i        => rxd_i,                           -- directly from pad - not yet associated with any time domain
                     rxd_clk_rx   => rxd_clk_rx,                      -- RXD synchronized to clk_rx
                     rx_data      => rx_data,                         -- 8 bit data output valid when rx_data_rdy is asserted
                     rx_data_rdy  => rx_data_rdy,                     -- active high signal indicating rx_data is valid
                     frm_err      => open                             -- framing error - active high when STOP bit not detected
                    );      

When I do the following command after opening the synthesized or implemented design, I get the correct value

get_property BAUD_RATE [get_cells uart_rx_i0]
115200

Avrum

[mvanderw]

I'd love to use this idea.  The "get property" works fine for me in the elaborated design - I can see all my VHDL generics show up as cell properties.  However in my synthesized design or implemented design, they are not there - just the basic properties.  I'm wondering if certain settings need to be set for synthesis in order make them visible.  I'm using the Vivado 2016.4 GUI. 

Thanks,

Mike

Edit: Resolved - must set flatten_hierarchy to "none" instead of "rebuilt" in project settings