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Observer redted
Registered: ‎04-04-2013

Get_tiles -of $tile, find out wich logic tiles are connected to an interconnect tile

For Virtex 7 devices one can run the following: 

get_tiles -of $logic_tile_object  #get the interconnect tile/null tiles related to the BRAM/CLB/DSP
get_tiles -of $null_tile_object #get the DSP/BRAM represented by the null tile
get_tiles -of $interconnect_tile_object #get the DSP/BRAM connected to the interconnect tile and the interconnect tile

However, on Ultrascale the return values appear to make less sense, i.e. for the interconnect tile INT_X5Y170 on xczu3eg, one gets the interconnect tile and tile CLEL_R_X5Y170, the CLB connected to the right side of the tile. One would expect that the CLB tile on the left CLEL_L_X5Y170 would be returned as well, as it is connected to the same interconnect tile.

I am wondering, what is the correct way to figure out which logic tiles are connected to an interconnect tile and vice versa (what are the interconnect tiles belonging to the logic tiles) for ultrascale designs?

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