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Explorer
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Registered: ‎05-25-2016

Help with component.xml absolute paths

Hello,

 

I've been reading through everything I can find on the forums to try to figure this out and I am stuck.  The below forum post below best describes where I am.

https://forums.xilinx.com/t5/Design-Entry/Is-it-possible-in-Vivado-to-package-a-custom-IP-with-relative/td-p/488200

 

My top level Vivado project uses a TCL for version control so it can be rebuilt without storing all the meta data for a vivado project - this is recommended by Xilinx.  It has a TCL script to create the vivado project itself and a TCL script for the BD.  There are also constraints at this level and then a directory for my IP cores.  I"ve gotten a lot of this working, but I'm stuck on the component.xml absolute paths.

 

An example of my directory structure looks like this:

 

Root dir -> Build_Vivado Proj.TCL

              -> BlockDiagram.TCL

              -> Constraints.xdc

               -> ip_repo -> MotorDriver  -> HDL

                                                         -> ip_package

                                                         -> working_project     

                               -> SPI Controller 

 

So my root directory contains two TCL scripts used to rebuild the project, constraints and a directory for all my IP.  Inside "ip_repo" I have all of my IP core subdirectories.  Inside the IP core subdirectory (for example in the motor controller IP core) I have a directory for all the HDL source which is version controlled, a directory for the final packaged IP files that are version controlled and the "working project" directory which only has a version controlled TCL script for rebuildig the project.  The working project directory is where I develop, simulate and updated the IP core.  In the working directory there is a script that builds the vivado project and pulls in the source code from the HDL directory.  This basically is a normal project that allows me to develop the HDL and keep it all together in the HDL directory.  So my vivado project in the working project folder links to the source HDL in the HDL folder.  This setup seems to be pretty VCS friendly (I'm using git) because at this point there are no binaries and there is no Vivado project metadata and project files. Once I'm happy with the code in my working directory I use the tools menu in Vivado to package the IP and place it in the "ip_package" diretory.

 

 

The issue I'm stuck on is this.

Because my source HDL is linked to my working project (in the working_project) directory, it uses absolute paths when produceing the "packaged" IP by using package IP in vivado.  This is apparently common knowledge and due to the fact that my HDL source code is linked outside of my working vivado project's root directory.  Discussion here:

https://forums.xilinx.com/t5/Design-Entry/Is-it-possible-in-Vivado-to-package-a-custom-IP-with-relative/td-p/488200

 

Has any progress been made here? some of these posts are old and I feel like I'm missing something or this is a dead end.  I can't find any other solution anywhere other than put your source code in the ".srcs" folder inside the vivado project diretory or modify X amount of component.xml files (one for each ip core).  The problem with this is that I don't know how to version control this easily and use TCL scripts (Xilinx recommendation for VCS) in a clean manner by using the "keep in the vivado project root directory" approach.  What i have right now is great other than this component.xml.  

 

So long story short, is the result of this post:

https://forums.xilinx.com/t5/Design-Entry/Is-it-possible-in-Vivado-to-package-a-custom-IP-with-relative/td-p/488200

 

to either change the component.xml files manually or place your source code in the root directory of my working vivado project for the IP core (in this example motor_controller->working_project)?  It seems like I'm 90% (or more) of the way there to a good VCS friendly Vivado project with the GUI except for this.

 

Hopefully this isn't too confusing, but unfortunatley the process is kind of involved.  Maybe this approach will help clarify things for other users confused about project VCS as well. 

 

                      

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