02-27-2017 09:19 AM
I am using Vivado 2016.1 and I would like to do the routing between two logic resources located in different slices and CLBs. I know that this routing must pass through different switch matrixes and logic resources and I know it is possible to do it via constraints definition. I have read UG894 and UG895 but they are so extensive and complicated ! Can anybody provide me a simple example of routing between two flip-flops to extend it for my own purpose?
P.S. : Previously this task was feasible in ISE FPGA Editor by Manual routing and I know it is possible in Vivado using scripts.
Kind replies are in advance appreciated.
02-27-2017 06:35 PM
02-27-2017 08:24 PM
I think "manual routing" section at page-122 of https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_4/ug904-vivado-implementation.pdf will be helpful to you.
02-28-2017 07:32 AM
Both your suggestions are helpful thank you ! But, the way mentioned in UG904 (page 122 to 144) are for "Manual Routing". I am curious to know how can I write the relevant script in *.tcl file and run it and it will do the automatic routing between a source and a destination define in *.tcl file?
To make it simple, please see the simple routing between two flip-flops shown in the attachment. I can see the Direct routing constraint obtained by the tool as follows:
CLBLL_LL_BQ CLBLL_LOGIC_OUTS5 WW2BEG1 ER1BEG2 EL1BEG1 BYP_ALT1 BYP_L1 CLBLL_LL_AX
Now, the question is that how can I import (or write) this routing constraint in *.tcl file and run it to do that routing automatically:? If this is possble, then we can control the routing path (which I think is feasible).
02-28-2017 08:27 PM
After manual routing, save the design in vivado. This will write out the constraints to target XDC file (which you can use in TCL).