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Observer andoki
Observer
1,205 Views
Registered: ‎11-19-2017

How to include Verilog file that has path as well

I wonder if Vivado does handle including file with path, such as "`include "fifo_128/fifo128_stub.v". Synthesizer can do, but other IP integrator or project handling command does not.

-- For example --

I have a set of files under some path, say

/home/user/my_project/fifos/fifo_128/fifo128_stub.v

/home/user/my_project/fifos/fifo_256/fifo256_stub.v

/home/user/my_project/fifos/fifo_512/fifo512_stub.v

Then, I have a Verilog design file that includes those files as follows

[my_design.v]

`include "fifo_128/fifo128_stub.v"

`include "fifo_128/fifo256_stub.v"

`include "fifo_128/fifo512_stub.v"

module my_design ( .... ); ..... endmodule

 

When I try to packaing IP, Vivado complaines about cannot find the files.

I cerainly add the directory in 'Verilog options' of Settings: Verilog Include Files Search Paths, in which "/home/user/my_project/fifos" is listed.

Are soulutions?

 

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1 Reply
Xilinx Employee
Xilinx Employee
1,177 Views
Registered: ‎05-22-2018

Re: How to include Verilog file that has path as well

Hi @andoki ,

 

Please check this link:

https://www.xilinx.com/support/answers/54006.html

Also try to give the whole path in `include command that should work.

Thanks,

Raj

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