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Visitor sebwerner
Visitor
10,984 Views
Registered: ‎07-21-2014

ILA post synthesis flow

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Hi everyone,

I'm trying to integrate the ILA 4.0 core into my design. I don't want to instantiate a module in my hdl code, i want to insert teh core in my nelist.

1.Before Synthesis i generate the core from the IP catalog

2. Then i synthesize the design

3. Then i customize the ILA core with the 'set up debug' option.

 

Everything is fine, but when i start the implementation is get the critical warning:

 

[Designutils 20-1281] Could not find module 'ila_0'. The XDC file project/project.srcs/sources_1/ip/ila_0/constraints/ila.xdc will not be read for this module.

Why is this warning coming?  And more importantly, will it have influences on my design later? How can i prevent that warning?

 

Best wishes

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Xilinx Employee
Xilinx Employee
19,280 Views
Registered: ‎09-20-2012

Re: ILA post synthesis flow

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Hi,

 

1.Before Synthesis i generate the core from the IP catalog

2. Then i synthesize the design

3. Then i customize the ILA core with the 'set up debug' option.

 


I dont think there is a need here to generate the ILA core at first. As you are using netlist insertion method of inserting the cores in design, you can use "MARK_DEBUG" attribute in HDL to preserve the signals for debug and later perform "setup debug" on synthesized design. This automatically inserts debug cores in the design.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
10,973 Views
Registered: ‎09-14-2007

Re: ILA post synthesis flow

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Hi,

 

Seems like you are not doing anything incorrect, although for some reason the core is not being seen.

 

Is there anyways you can share the design?

 

Thanks

Duth

 

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Xilinx Employee
Xilinx Employee
19,281 Views
Registered: ‎09-20-2012

Re: ILA post synthesis flow

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Hi,

 

1.Before Synthesis i generate the core from the IP catalog

2. Then i synthesize the design

3. Then i customize the ILA core with the 'set up debug' option.

 


I dont think there is a need here to generate the ILA core at first. As you are using netlist insertion method of inserting the cores in design, you can use "MARK_DEBUG" attribute in HDL to preserve the signals for debug and later perform "setup debug" on synthesized design. This automatically inserts debug cores in the design.

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
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Moderator
Moderator
10,956 Views
Registered: ‎01-16-2013

Re: ILA post synthesis flow

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Visitor sebwerner
Visitor
10,949 Views
Registered: ‎07-21-2014

Re: ILA post synthesis flow

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Thank you all a lot.

 

I think the issue here is that in case i generate the ILA IP before synthesis, the tool expects an instantiation of it in my design. As there is no module definition/or instantiation of the ILA core (because i use the post-synthesis flow), the module is not detected and thus the critical warning.

 

If i instantiate the module or don't generate the cores before synthesis, the warning doesn't occur.

 

Best wishes

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