05-15-2013 12:00 PM
This post talks about editing an IP Integrator block diagram in tcl and then loading it in the project. I'm looking for documentation for the opposite. How do you edit a block diagram in the GUI and then include it in a non-project batch flow? I can't seem to find documentation for commands such as read_verilog / read_vhdl that would read a bd into memory.
Are you required to use a project based flow with IP Integrator?
05-15-2013 02:21 PM
We are still working on a lot of this collateral. Currently an IPI subsystem does not make sense in a non-project flow, because of the dynamic nature of the generation architecture. One thing that is there however is to take a bd designed wiht the GUI and exporting a tcl script that will reproduce it. This can be used in a non-project flow.
Please see write_bd_tcl Tcl command. This is still in development, but it should be documented in the help and the Tcl command reference.
05-16-2013 09:05 AM
OK, that makes sense, thank you. Also, it seems it would be much easier to check in a tcl script. I have viewed your webinar and materials about working with revision control, and it recommended against keeping sources in your project, and against checking in a project directory. I tried taking the .bd file out of the directory but it seems there are other dependency files that didn't work so well with.
With this flow it seems you could make a new project, create a .bd, export the tcl, and then run the build from the tcl script which is checked in.
05-16-2013 10:50 AM
So, write_bd_tcl works, and I can source the tcl file in a project to recreate the diagram (provided you have your IP repositories mapped beforehand).
I am trying this in a non-project flow now, and when I source the block diagram (in the Vivado TCL prompt), I get this:
ERROR: [IP_Flow 19-2180] The specified IP 'xilinx.com:ip:processing_system7:5.01' does not support the current part 'xc7vx485ttffg1157-1'
This is because that's just the 'default' part - Normally the part number comes into play in the non-project mode when you run synthesis:
synth_design -top design_1_wrapper.v -part xc7z020clg484-1
However, I need to source the block diagram first.
Is there some TCL command to set the part? I can't find one.
05-20-2013 12:23 PM
Yes and no.
First of all, let me start by telling you that the IP and IPI flows are not fully architected to support the non-project flows, because they deliver a lot of files: parameterized HDL, constraints, simulation testbenches, example designs, documentation, etc... The non-project flow is meant for things that really can be compiled in memory - and IP is just not naturally that way - and therefore neither is IPI. So you really will be thinking about how to create a project via Tcl - and this where the write_project_tcl comes in - and again you can create a tcl script to recreate the project just as you can in non-project mode.
Next, I'll also let you in on a small secret/nuance. There is always a project. Even for the non-project flows - there is a small in-memory representation of a project so that we can make all the commands behave consistently in project and nonproject flows - the main difference is there is nothing traditionally saved to disk (like the .xpr and all the directories and sources) in a netlist or rtl compilation flow. So there is a hidden, non-documented option to create_project which is implicitly run for you when you "bootstrap" a non-project design with synth_design -part for RTL or link_design -part for a netlist design.
For IP or IPI, we are still working out the flows - so you can use this command - but be aware that our primary recommendation at this time is to use project-based flows with IPI and IP, but this should get you a little farther along the non-project flow with IPI if you still wish to try:
create_project -part foo -in_memory
The other thing you can do - similar result but slightly different way to do that - is to add a source or read a RTL file first - which will implicitly create the in-memory project. If you do this (for example read_verilog foo.v) you will notice that there is now magically a project in memory called "New Project" - not on disk). You can then set the part with a set_property command
set_property PART <your_chosen_part> [current_project]
I know this is not clean. We are working on the API for IPI as i said, so this is the best guidance I can give you at this time. A project-based flow is the best long-term solution if you are concerned about having to change your scripts at some point in the future if you use one of the above workarounds.
09-14-2013 02:36 PM
It seems when you try to source a file generated from write_bd_tcl in non-project mode, it generates a .srcs and .Xil folder and pulls all the IP into the .srcs folder. This doesn't seem consistent with 'non-project mode is entirely in RAM'. Are you sure we are still in non-project mode here?
05-29-2014 07:05 PM
This link will give you the details of non-project mode options http://www.xilinx.com/training/vivado/using-the-non-project-batch-flow.htm
Vivado Design flows documents