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Observer jahogan
Observer
3,933 Views
Registered: ‎11-06-2012

Non-project Mode Synthesis read_verilog

 

I am processing a design using non-project mode and encountered the following synthesis error when reading the design source files using the tcl commands shown:

 

 

read_verilog [glob E:/Scripted/proj/src/verilog/*.v]
read_vhdl [glob E:/Scripted/proj/src/vhdl/*.vhd]
ERROR: [Synth 8-660] unable to resolve 'clog2s' [E:/Scripted/proj/src/verilog/wrapper_vc707.v:143]

 

clog2s is a function defined in a Verilog header file, the path to which is passed to the synthesis process using the -include_dirs flag.

 

The above error is resolved by instead reading the design source files as shown below:

 

read_verilog E:/Scripted/proj/src/verilog/<any_file>.v
read_verilog [glob E:/Scripted/proj/src/verilog/*.v]
read_vhdl [glob E:/Scripted/proj/src/vhdl/*.vhd]

 

Can someone who is more familiar with the Vivado tools explain why directly reading a single Verilog source file prior to reading a group of source files seemingly impacts the tool's ability to resolve Verilog functions included in Verilog header files?  Perhaps I have missed something basic about the non-project mode design flow...

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4 Replies
Xilinx Employee
Xilinx Employee
3,921 Views
Registered: ‎04-16-2008

Re: Non-project Mode Synthesis read_verilog

Hi @jahogan

 

I don't have a clear answer as to why this occurs. It may be a bug with the way read_* commands work on a list. It seems like it isn't doing the same processing on a list of files like it does for an individual file. If you look at the properties on the header file between the two methods, this may give some additional clue as to what is happening.

report_property [get_files file_name.v]

 

For instance you  may find that the individual 'read_verilog' command automatically sets FILE_TYPE property as {Verilog Header}, while the 'glob' approach does not.  In that case you could probably make this work by manually setting the FILE_TYPE property on files that are Verilog Header files.

 

Alternatively, if you want to use a single [glob] to work, you may try doing it this way:

foreach file [glob E:/Scripted/proj/src/verilog/*.v] {
   read_verilog $file
}

I believe Vivado also treats the files differently based on extension, so you could try renaming the verilog file to ".vh", and this may solve the issue as well.

 

Hope these helps, and that one of these solutions gets you closer to what you want.

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Observer jahogan
Observer
3,919 Views
Registered: ‎11-06-2012

Re: Non-project Mode Synthesis read_verilog

Thanks @woodsd,

I should specify that argument to the added read_verilog call (i.e. <any_file.v>) is one of the Verilog source files. It's not the Verilog header file. All the Verilog header files are still passed to the tool using the -include_dirs flag.

I agree that it appears that read_verilog processes list arguments differently than individual files. The error seems to be resolved, but I wanted to see if there was an obvious root cause.

I also just wanted to post what I observed. It was a nightmare to resolve because based on the provided error message it seemed that the problem was with the -include_dirs behavior. It doesn't appear to have anything to do with the inclusion of the header files.




J
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Xilinx Employee
Xilinx Employee
3,910 Views
Registered: ‎04-16-2008

Re: Non-project Mode Synthesis read_verilog

Hi @jahogan

 

Are these source files you could share with Xilinx? Could you archive them along with a "works.tcl" and "fails.tcl" that shows the differences between the two methodologies?  

 

If you are able to share these, I can give you instructions on how to securely transfer the testcase to me, and I'll get a Change Request (CR) filed against the tools with this testcase.  

 

 

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Observer jahogan
Observer
3,902 Views
Registered: ‎11-06-2012

Re: Non-project Mode Synthesis read_verilog

Yes, I can share...
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