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Visitor
Visitor
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Registered: ‎03-19-2019

Problem with DPLL counter and clock divider

Hello Xilinx Team,

when generating the hdf file, we get the following part of the function dpll_prog() generated, but we don't want to have the dividers set (It shall NOT divide).

Problem is:

We get half of the DPLL frequency set, as required by using the Vivado tool.

Currently we are uncommenting the following lines in psu_init.c after generation:

static void dpll_prog(int ddr_pll_fbdiv, int d_lock_dly, int d_lock_cnt,
 int d_lfhf, int d_cp, int d_res) {
 unsigned int pll_ctrl_regval;
 unsigned int pll_status_regval;
#if 0 // The following block has been disabled manually by Continental because it is wrongly generated pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CTRL);
 pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CTRL_DIV2_MASK);
 pll_ctrl_regval = pll_ctrl_regval | (1 << CRF_APB_DPLL_CTRL_DIV2_SHIFT);
 Xil_Out32(CRF_APB_DPLL_CTRL, pll_ctrl_regval);
#endif // #if 0 // The following block has been disabled...

 

-> Is this problem known to you ?

-> Do you plan to have a solution for it ?

 

Br,

J. Auer

(ADAS Neu-Ulm)

 

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Visitor
Visitor
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Registered: ‎03-19-2019

Re: Problem with DPLL counter and clock divider

Additional information.

Vivado input mask addded.

VivadoMask1.jpg
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