06-16-2017 01:27 AM
I have a problem with using timing constraints in Xilinx 2014.
Above capture is my problem.
I made a '.xdc' file for control MAX clock frequency & set timing constraints to 600MHz.
(My program is so simple toy-example, so I think that of click frequency doesn't make problem )
Anyway, the result of Pulse Width is fine, but else part(Setup and Hold part) show 'NA'!
What is the meaning of 'NA'? and how can i fix that problem?
please, i hope someone help me..
06-16-2017 02:26 AM - edited 06-16-2017 02:53 AM
Check the following forum post:
Can you please share the vivado.log and also the XDC file?
06-18-2017 06:04 PM
06-18-2017 06:26 PM
You don't have register-to-register timing paths so your create_clock constraint does not cover any timing paths.
Actually you only have PAD-to-register and register-to-PAD paths, which are covered by input delay and output delay constraints.
If you'd like to evaluate the max frequency, you need to add at least an extra level of registers in the design.