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Visitor
Visitor
3,755 Views
Registered: ‎06-16-2017

Problem with using Timing Constraints

Hi, everyone.

 

I have a problem with using timing constraints in Xilinx 2014.

 

qq.jpg

 

Above capture is my problem.

 

I made a '.xdc' file for control MAX clock frequency & set timing constraints to 600MHz.

(My program is so simple toy-example, so I think that of click frequency doesn't make problem )

 

Anyway, the result of Pulse Width is fine, but else part(Setup and Hold part) show 'NA'!

What is the meaning of 'NA'? and how can i fix that problem?

 

please, i hope someone help me..

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5 Replies
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Explorer
Explorer
3,748 Views
Registered: ‎04-12-2017

I think you should state which device are you using.

Avi Chami MSc
FPGA Site
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Moderator
Moderator
3,730 Views
Registered: ‎01-16-2013

@yss12114,


Check the following forum post:

https://forums.xilinx.com/t5/Timing-Analysis/NA-in-timing-report-after-implementation/td-p/653040

 

Can you please share the vivado.log and also the XDC file?

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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Visitor
Visitor
3,665 Views
Registered: ‎06-16-2017

제목 없음.jpg

 

↑Is above what you want?

 

In addition, I use Vivado 2014.4 tool..

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Visitor
Visitor
3,662 Views
Registered: ‎06-16-2017

Thanks for your help, but the solution you told me doesn,t work..

 

And,

 

I attach those project file(project_MMS_CNU), test bench file(TB), constraint file(TT).

 

Check these files, please!

 

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Xilinx Employee
Xilinx Employee
3,658 Views
Registered: ‎05-14-2008

You don't have register-to-register timing paths so your create_clock constraint does not cover any timing paths.

Actually you only have PAD-to-register and register-to-PAD paths, which are covered by input delay and output delay constraints.

 

If you'd like to evaluate the max frequency, you need to add at least an extra level of registers in the design.

 

Thanks

Vivian

 

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