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Observer saju
Observer
8,497 Views
Registered: ‎07-30-2016

Property to get net delay

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Hi,

I have a Kintex ultrascale design, with some timing violations.

One of the reasons - are nets that have large delay (due to fanout and/or placement and/or congestion detours).

I wanted to get all nets with delay > user-defined-threshold.

In that context, was looking at the PROPERTY values associated with nets/cells/pins.

But, it appears that Xilinx does not have net--delay PROPERTY stored.

Is there any way to get this information ?

 

The report_timing gives this net delay, but, then, it it is a cumbersome process -  and we may miss to see all nets - unless they result in a timing violation - and also will require a post-processing script.

 

Regards,

- Saju

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Guide avrumw
Guide
14,952 Views
Registered: ‎01-23-2009

Re: Property to get net delay

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Thanks Avrum, You got the crux of the problem - it becomes an O(N2) complexity problem with 2 iterative loops for all nets, and for all pins on that net.

 

So, it is O(N^2) since the number of nets in a design is O(N^2). However, it isn't really two iterative loops - the command I gave you returns the SLOW_MAX for all net_delays on a net (hence for all destination pins) and can even filter to only give you the values greater than a threshold, so the "iteration on the pins within the net" is done internally to the command. You would then need to iterate on each net.

 

Can I get the alternate way, ie iterate thru ALL  the pins of the design ?

 

Whether you do it by pin or by net, it will still be the same number of net delays. Doing it by pin doesn't actually seem to be possible (it still needs the -of_objects <net>, so what I have given you is what you have). Furthermore, doing it by net will be faster. The operation of a Vivado database command is actually pretty fast. The slow operation is initiating the Tcl command and/or transferring data to and from the Tcl interpreter. So the command I gave you processes all the net_delays on one net "internally", and is thus one command for each net in the design. Doing the command by pin, you would need one Tcl command per pin, which would be much slower.

 

Is there a way to get the SLOW_MAX property for that net

 

I am not sure what you are asking here. The command to get the SLOW_MAX on all net_delays on a net would be

 

get_property SLOW_MAX [get_net_delays -of_objects [get_nets <net_name]]

 

This will return a list of the SLOW_MAX values. You could sort this with lsort if you wanted, and get the worst one with lindex after that:

 

lindex [lsort [get_property SLOW_MAX [get_net_delays -of_objects [get_nets uart_rx_i0/uart_baud_gen_rx_i0/baud_x16_en ]]]] 0

 

Another related question/clarification:...

 

The interconnect network in the FPGA is fully buffered, so there is never a problem with transition time or signal integrity/degradation - net delay is just delay.

 

Also, I am not sure why you are really looking at net delays. Net delay on its own isn't a problem - it's only a problem if it causes a path to violate. You may have a really long net delay that does not cause a violation (if there is little else on the path), or you could have only an only slightly long net delay on a path with other stuff on it that does create a violation. So, really you should just focus on the failing paths, rather than a blanket approach to decreasing net delays...

 

Avrum

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7 Replies
Xilinx Employee
Xilinx Employee
8,495 Views
Registered: ‎08-01-2008

Re: Property to get net delay

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check this ARs
http://www.xilinx.com/support/answers/65408.html

check this Guide

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug906-vivado-design-analysis.pdf

 

This is one related ARs

http://www.xilinx.com/support/answers/59176.html

Thanks and Regards
Balkrishan
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Xilinx Employee
Xilinx Employee
8,481 Views
Registered: ‎08-01-2008

Re: Property to get net delay

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use tcl guide for tcl commends
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_1/ug835-vivado-tcl-commands.pdf
Thanks and Regards
Balkrishan
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Xilinx Employee
Xilinx Employee
8,463 Views
Registered: ‎05-07-2015

Re: Property to get net delay

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HI @saju

 

Though there is  No  ready to use tcl command to get nets of delays highger than a  value.

There is way to get all the high fan out nets (which generally have high net delays)

 

"report_high_fanout_nets" is tcl command to use
you can even report nets with any fanout using -fanout_lesser_than and  -fanout_greater_than  options of this tcl command.

Thanks
Bharath
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Guide avrumw
Guide
8,445 Views
Registered: ‎01-23-2009

Re: Property to get net delay

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Saju,

 

I don't think this is going to be something you want to do...

 

First, you have to realize that nets have more than one net_delay; if a net has one driver and 100 receivers then there are 100 individual net delays associated with that one net. You can get the net delays of a net using

 

set net_delays [get_net_delays -of_objects [get_nets <net_name>]]

 

This returns a list of "net_delay" objects - in my example above this command would return a list of 100 net_delay objects into the Tcl variable net_delay.

 

Like other objects, net_delay objects have properties - you can see the properties of one such object by using the command

 

report_property [lindex $net_delays 0]

 

This will show something like

 

report_property [lindex $net_delays 0]
Property   Type    Read-only  Value
CLASS      string  true       net_delay
ESTIMATED  bool    true       0
FAST_MAX   int     true       498
FAST_MIN   int     true       417
NAME       string  true       uart_rx_i0/uart_baud_gen_rx_i0/baud_x16_en_to_uart_rx_i0/uart_rx_ctl_i0/over_sample_cnt[2]_i_2/I0
NET        string  true       uart_rx_i0/uart_baud_gen_rx_i0/baud_x16_en
SLOW_MAX   int     true       791
SLOW_MIN   int     true       665
TO_PIN     string  true       uart_rx_i0/uart_rx_ctl_i0/over_sample_cnt[2]_i_2/I0

One of the properties is the delay (in picoseconds) of the net in the four process corners. I presume you are most interested in SLOW_MAX, so you could do

 

get_property SLOW_MAX [lindex $net_delays 0]

 

To get the delay of that arc.

 

You can even do a filter command on SLOW_MAX to get the big ones. For example

 

set big_net_delays [get_net_delays -of_objects [get_nets uart_rx_i0/uart_baud_gen_rx_i0/baud_x16_en ] -filter {SLOW_MAX > 750} ]

 

which will return only net delays of this net that has a SLOW_MAX delay greater than 750ps.

 

However, I don't think you can do this for the whole design...

 

The get_net_delays command must use the -of_objects option (its the only get_* command that I know of that has this restriction). Furthermore, (and even though the help page for this command implies otherwise), the -of_objects "list" must contain one and only one net. So, you can do this only for one net at a time.

 

In theory, you could do this in a foreach loop using [get_nets -hier], but processing the huge number of nets in a design in a Tcl loop is going to take forever...

 

Avrum

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Observer saju
Observer
8,419 Views
Registered: ‎07-30-2016

Re: Property to get net delay

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Thanks Avrum, You got the crux of the problem - it becomes an O(N2) complexity problem with 2 iterative loops for all nets, and for all pins on that net.

Can I get the alternate way, ie iterate thru ALL  the pins of the design ?

Is there a way to get the SLOW_MAX property for that net

 

Another related question/clarification:

Even in the cases where the net-delay values are high, it does not mean that the transition time of the net is bad, since the delay is just a cumulative delay through various switch-boxes and they ensure that the net is adequately buffered,  right ?

I would like to ensure that there is no signal quality degradation..

 

Regards,

- Saju

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Guide avrumw
Guide
14,953 Views
Registered: ‎01-23-2009

Re: Property to get net delay

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Thanks Avrum, You got the crux of the problem - it becomes an O(N2) complexity problem with 2 iterative loops for all nets, and for all pins on that net.

 

So, it is O(N^2) since the number of nets in a design is O(N^2). However, it isn't really two iterative loops - the command I gave you returns the SLOW_MAX for all net_delays on a net (hence for all destination pins) and can even filter to only give you the values greater than a threshold, so the "iteration on the pins within the net" is done internally to the command. You would then need to iterate on each net.

 

Can I get the alternate way, ie iterate thru ALL  the pins of the design ?

 

Whether you do it by pin or by net, it will still be the same number of net delays. Doing it by pin doesn't actually seem to be possible (it still needs the -of_objects <net>, so what I have given you is what you have). Furthermore, doing it by net will be faster. The operation of a Vivado database command is actually pretty fast. The slow operation is initiating the Tcl command and/or transferring data to and from the Tcl interpreter. So the command I gave you processes all the net_delays on one net "internally", and is thus one command for each net in the design. Doing the command by pin, you would need one Tcl command per pin, which would be much slower.

 

Is there a way to get the SLOW_MAX property for that net

 

I am not sure what you are asking here. The command to get the SLOW_MAX on all net_delays on a net would be

 

get_property SLOW_MAX [get_net_delays -of_objects [get_nets <net_name]]

 

This will return a list of the SLOW_MAX values. You could sort this with lsort if you wanted, and get the worst one with lindex after that:

 

lindex [lsort [get_property SLOW_MAX [get_net_delays -of_objects [get_nets uart_rx_i0/uart_baud_gen_rx_i0/baud_x16_en ]]]] 0

 

Another related question/clarification:...

 

The interconnect network in the FPGA is fully buffered, so there is never a problem with transition time or signal integrity/degradation - net delay is just delay.

 

Also, I am not sure why you are really looking at net delays. Net delay on its own isn't a problem - it's only a problem if it causes a path to violate. You may have a really long net delay that does not cause a violation (if there is little else on the path), or you could have only an only slightly long net delay on a path with other stuff on it that does create a violation. So, really you should just focus on the failing paths, rather than a blanket approach to decreasing net delays...

 

Avrum

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Observer saju
Observer
8,248 Views
Registered: ‎07-30-2016

Re: Property to get net delay

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Thanks Avrum -  for your detailed explanation, and the script snippets.

Currently, our design has quite a few timing paths that violate, with path delay being dominated by net delay (80%+), compared to logic/LUT delay (only 20%). 

This was the reason why we wanted to get high net-delay nets.

We are trying to do HF net replication and other techniques .

 

Regards,

- Saju.

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