cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
tsung
Visitor
Visitor
349 Views
Registered: ‎10-30-2020

RLOC_ORIGIN physical constraint is not honored from VHDL code

In order to physically constrained my design using RLOC/RLOC_ORIGIN. Following are the VHDL code from my top level modules

-----
attribute RLOC_ORIGIN: string;
attribute RLOC: string;
attribute RLOC of SLICE_X1Y0: label is "X0Y0";
attribute RLOC of SLICE_X1Y2: label is "X0Y2";
attribute RLOC_ORIGIN of SLICE_X1Y0: label is "X1Y0";

----

Two instances "SLICE_X1Y0" and "SLICE_X1Y2" which has the name equal to the SLICE coordination that I intend to place. However, when I checked the design from GUI, it seems to me the RLOC constraints was honored but not the "RLOC_ORIGIN".

I use the "Vivado" version 2018.3 and the target device is "xc7s100fgga676-1"

Following is the screen dump of the design, as you can clearly see those 2 design instances are not located at the bottom/left corner as they should be.

 

 

Screen Shot 2021-03-29 at 11.39.38 AM.png
0 Kudos
7 Replies
richardhead
Scholar
Scholar
346 Views
Registered: ‎08-01-2012

IIRC, Vivado does not accept constraints written in HDL code. You will need to apply RLOCs as part of the project in constraints.

0 Kudos
tsung
Visitor
Visitor
345 Views
Registered: ‎10-30-2020

Thanks for the help. Can you point me some document in order to constraint in the project.

0 Kudos
richardhead
Scholar
Scholar
307 Views
Registered: ‎08-01-2012

OK - I was wrong - it appears it should be possible. But it needs to be applied to signals - you appear to be trying to apply it directly to entities?

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug903-vivado-using-constraints.pdf

0 Kudos
tsung
Visitor
Visitor
302 Views
Registered: ‎10-30-2020

This is what I do following this document.

In the page 167, I applied the "RLOC_ORIGIN" at the particular cells as indicated by this document. Then, I found this issue which RLOC_ORIGIN is not honored.

 

Screen Shot 2021-03-29 at 1.21.39 PM.png
0 Kudos
tsung
Visitor
Visitor
286 Views
Registered: ‎10-30-2020

After the design is synthesized, the .dcp is reading in, there is this "critical warning" which is confused to me. [Constraints 18-432]. Vivado seem to look for "RLOC_X0Y0" which does not exist on my design.

 

Screen Shot 2021-03-29 at 1.45.53 PM.png
0 Kudos
richardhead
Scholar
Scholar
277 Views
Registered: ‎08-01-2012

Is it possible is was removed during synthesis?

I notice you are applying the attribute to a label - can you post the original code?

0 Kudos
tsung
Visitor
Visitor
249 Views
Registered: ‎10-30-2020

Thanks for helping.

Yes, the constraint is removed during synthesis. I am uploading my design files into this ticket. Please find the tar file - rloc_origin_issue.tar.gz. There is a script in the test case - run_vivado. There is one blackbox cell definition under directory "slice/plb.edf".

0 Kudos