03-29-2021 08:54 AM
In order to physically constrained my design using RLOC/RLOC_ORIGIN. Following are the VHDL code from my top level modules
attribute RLOC_ORIGIN: string;
attribute RLOC: string;
attribute RLOC of SLICE_X1Y0: label is "X0Y0";
attribute RLOC of SLICE_X1Y2: label is "X0Y2";
attribute RLOC_ORIGIN of SLICE_X1Y0: label is "X1Y0";
Two instances "SLICE_X1Y0" and "SLICE_X1Y2" which has the name equal to the SLICE coordination that I intend to place. However, when I checked the design from GUI, it seems to me the RLOC constraints was honored but not the "RLOC_ORIGIN".
I use the "Vivado" version 2018.3 and the target device is "xc7s100fgga676-1"
Following is the screen dump of the design, as you can clearly see those 2 design instances are not located at the bottom/left corner as they should be.
03-29-2021 10:15 AM - edited 03-29-2021 10:15 AM
OK - I was wrong - it appears it should be possible. But it needs to be applied to signals - you appear to be trying to apply it directly to entities?
03-29-2021 10:26 AM
This is what I do following this document.
In the page 167, I applied the "RLOC_ORIGIN" at the particular cells as indicated by this document. Then, I found this issue which RLOC_ORIGIN is not honored.
03-29-2021 10:52 AM
After the design is synthesized, the .dcp is reading in, there is this "critical warning" which is confused to me. [Constraints 18-432]. Vivado seem to look for "RLOC_X0Y0" which does not exist on my design.
03-29-2021 01:14 PM