03-08-2019 01:25 AM
I am working in vivado, and when running the RTL schematic I ran into a problem.
One of my vhd modules are apparently a black box type. I have no idea how that happened, and I can't click on the the module in my schematic to see what's inside.
How do I fix that?
03-08-2019 02:49 AM
The reason for module coming as Black Box can be that the Vivado is unable to make a connection between the instantiation and the module. The first thing I would suggest is to check your syntax and verify that the instantiation exactly matches the module definition.
Also if you are building the design with "Out of Context" mode ("OCC"), then change that to use "Global".
03-08-2019 02:56 AM
In addition to the above, check if you have added the VHDL module to your Xilinx project.