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Observer
Observer
5,025 Views
Registered: ‎01-25-2017

Resizing pblocks through TCL gives warning Vivado 12-4775

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I have a Nexys 4 board and I'm trying to make it so that all of the leaf nodes of the top module are separated physically from all of the leaf nodes of the child module. I thought the best way to do this would be to create two different pblocks, add a mutually exclusive set of sites to each of them and then add the various cells to their respective pblock. This is part of an Out-Of-Context implementation of a design, thus the CONTAIN_ROUTING constraint.

#####################################################
# Create OOC pblock(s)
create_pblock pblock_counter
resize_pblock [get_pblocks pblock_counter] -add {SLICE_X52Y50:SLICE_X89Y99}
resize_pblock [get_pblocks pblock_counter] -add {DSP48_X1Y20:DSP48_X2Y39}
resize_pblock [get_pblocks pblock_counter] -add {RAMB18_X1Y20:RAMB18_X3Y39}
resize_pblock [get_pblocks pblock_counter] -add {RAMB36_X1Y10:RAMB36_X3Y19}
set_property CONTAIN_ROUTING 1 [get_pblocks pblock_counter]

#####################################################
# Create top pblock
create_pblock pblock_top
resize_pblock [get_pblocks pblock_top] -add [get_sites SLICE*];		#trying to add all usable sites
resize_pblock [get_pblocks pblock_top] -add [get_sites DSP*]
resize_pblock [get_pblocks pblock_top] -add [get_sites RAM*]
set_property CONTAIN_ROUTING 1 [get_pblocks pblock_top]

#####################################################
# Remove sites contained in the OOC pblock(s) from pblock_top
resize_pblock [get_pblocks pblock_top] -remove [get_sites -of_objects [get_pblocks pblock_counter]]

#####################################################
# Add all cells from the design to pblock_top
add_cells_to_pblock [get_pblocks pblock_top] [get_cells]

#####################################################
# Add cells from OOC modules to their respective pblocks
add_cells_to_pblock [get_pblocks pblock_counter] [get_cells counter0]; #This removes the cells from pblock_top

As you can see, I'm trying to do this all in such a way that I only have to modify the section labeled "Create OOC pblock(s)". However, I get warning [Vivado 12-4775] after I run the second line of the following block:

create_pblock pblock_top
resize_pblock [get_pblocks pblock_top] -add [get_sites SLICE*]
WARNING: [Vivado 12-4775] These ranges are not aligned to a tile boundary and will be extended to: SLICE_X1Y199:SLICE_X1Y199, SLICE_X0Y199:SLICE_X0Y199, SLICE_X2Y199:SLICE_X2Y199, SLICE_X3Y199:SLICE_X3Y199, SLICE_X5Y199:SLICE_X5Y199, SLICE_X4Y199:SLICE_X4Y199, SLICE_X6Y199:SLICE_X6Y199, SLICE...

Is there a better way to create physically distinct regions on the FPGA, such that no site is shared by two pblocks? I understand that this is just a warning and could have no effect on my design down the road. However, I believe it may be doing just that. (Essentially when I run an OOC implementation and open up the final top_route_design.dcp file, it only contains one pblock, and it's named counter0_pblock_counter, which leaves me with no clue as to what Vivado is doing with my design (where did the other pblock go?!?) and the xdc commands I gave it).

 

My goal here is to gain some wisdom from the TCL crowd about why I would get that warning and if there is a better way to try and do what I'm doing.

 

--byusean

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Xilinx Employee
Xilinx Employee
8,859 Views
Registered: ‎04-16-2008

Hi byusean,

 

This is not a recommended way to do this, and you will likely cause the placer a lot of confusion.  If your goal is to create phsycially isolated regions for each sub-module, and then leave the rest of the device for the remaining top-level logic, you should use EXCLUDE_PLACMENT on each of the sub-module Pblocks, and do NOT create a Pblock for "Top". 

 

Creating these EXCLUDE_PLACMENT Pblocks for the sub-modules will tell the placer to create an "internal" pblock for the rest of the logic that is everything except the sites owned by the EXCLDUE_PLACMENT pblocks.  I think this is what you are after.  This is how the Partial Reconfiguration flow works, FYI.  

 

Hope this helps.

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Xilinx Employee
Xilinx Employee
8,860 Views
Registered: ‎04-16-2008

Hi byusean,

 

This is not a recommended way to do this, and you will likely cause the placer a lot of confusion.  If your goal is to create phsycially isolated regions for each sub-module, and then leave the rest of the device for the remaining top-level logic, you should use EXCLUDE_PLACMENT on each of the sub-module Pblocks, and do NOT create a Pblock for "Top". 

 

Creating these EXCLUDE_PLACMENT Pblocks for the sub-modules will tell the placer to create an "internal" pblock for the rest of the logic that is everything except the sites owned by the EXCLDUE_PLACMENT pblocks.  I think this is what you are after.  This is how the Partial Reconfiguration flow works, FYI.  

 

Hope this helps.

View solution in original post

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Observer
Observer
4,998 Views
Registered: ‎01-25-2017

Thanks for the quick and accurate response.

In the attached image I've highlighted all of the leaf nodes from the top module. As you can see, they all lie outside of the pblock.

EXCLUDE_ROUTING.png

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