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Newbie lucarepetti
Newbie
248 Views
Registered: ‎03-04-2019

TCL Scripting assertion VHDL

Hello everyone,
I'm searching for a solution for auto-checking the results of the assertion in my vhdl benchmarks;

I'm mainly using this benchmark:

for {set i 1} {$i < 10} {incr i} {
    set_property top autogen_test_bench_$i [get_filesets sim_5]
    set_property top_lib xil_defaultlib [get_filesets sim_5]
    update_compile_order -fileset sim_5
    launch_simulation -mode behavioral
    run 10 us
    close_sim
    launch_simulation -mode post-synthesis -type functional
    run 10 us
    close_sim
    launch_simulation -mode post-synthesis -type timing
    run 10 us
    close_sim	
}

It scripts through a series of testbenches in sim_1, that ends up with different assertions if they end up correctly or not.
Is there a way to check into the script the assertion made, using some TCL commands? Would you recommend me something different from assertions, to use into testbenches, for this kind of work?
Thanks a lot in advance

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1 Reply
Moderator
Moderator
190 Views
Registered: ‎05-31-2017

Re: TCL Scripting assertion VHDL

Hi @lucarepetti ,

Are you looking to compare the values of the objects in the design with your golden values? If so, then you can use the get_value command specifying the object with it's scope in your TCL script

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