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Scholar chevalier
Scholar
14,178 Views
Registered: ‎10-07-2011

TCL/XDC: Renaming clocks

Jump to solution

Hi folks,

 

I'm using Vivado 2014.1 on Win7-64.

 

When PLL and MMCMs are used, a lot of secondary clocks are automatically-generated. When looking at the clock report, we can see the generated clocks all have very long not self-explanatory names. For example

report_clocks
*********************************************************************************************
* Report  : Clocks
* Design  : TopLevel
* Part    : Device=7vx690t, Package=ffg1761, Speed=-2
* Version : Vivado v2014.1 (64-bit) SW Build 881834 on Fri Apr  4 14:12:35 MDT 2014
* Date    : Thu May 01 16:20:16 2014
*********************************************************************************************


Attributes
  P: Propagated
  G: Generated
  V: Virtual
  I: Inverted

Clock                                                                                                                                                                                            Period    Waveform            Attributes  Sources
U8/U1/mdm_1/U0/Use_E2.BSCANE2_I/DRCK                                                                                                                                                             33.33300  {0.00000 16.66650}  P           {U8/U1/mdm_1/U0/Use_E2.BSCANE2_I/DRCK}
U8/U1/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE                                                                                                                                                           33.33300  {0.00000 16.66650}  P           {U8/U1/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE}
CLK_233MHz                                                                                                                                                                                       4.28800   {0.00000 2.14400}   P           {CLK_233MHz_P_AY18}
CLK_200MHz                                                                                                                                                                                       5.00000   {0.00000 2.50000}   P           {CLK_200MHz_P_H19}
CLKFBOUT                                                                                                                                                                                         5.00000   {0.00000 2.50000}   P,G         {U7/clk_wiz_0/U0/plle2_adv_inst/CLKFBOUT}
CLKOUT0                                                                                                                                                                                          5.00000   {0.00000 2.50000}   P,G         {U7/clk_wiz_0/U0/plle2_adv_inst/CLKOUT0}
CLKOUT1                                                                                                                                                                                          5.00000   {0.00000 2.50000}   P,G         {U7/clk_wiz_0/U0/plle2_adv_inst/CLKOUT1}
u_PlatformCore_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clkfbout                                                                                                                            4.28800   {0.00000 2.14400}   P,G         {U8/U1/mig_7series_0/u_PlatformCore_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT}
u_PlatformCore_mig_7series_0_0_mig/freq_refclk                                                                                                                                                   1.07200   {1.00500 1.54100}   P,G         {U8/U1/mig_7series_0/u_PlatformCore_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0}
u_PlatformCore_mig_7series_0_0_mig/mem_refclk                                                                                                                                                    1.07200   {0.00000 0.53600}   P,G         {U8/U1/mig_7series_0/u_PlatformCore_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1}
u_PlatformCore_mig_7series_0_0_mig/sync_pulse                                                                                                                                                    17.15200  {0.46900 1.54100}   P,G         {U8/U1/mig_7series_0/u_PlatformCore_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2}
u_PlatformCore_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out                                                                                                                            4.28800   {0.00000 2.14400}   P,G         {U8/U1/mig_7series_0/u_PlatformCore_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3}
u_PlatformCore_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk     1.07200   {1.00500 1.54100}   P,G         {U8/U1/mig_7series_0/u_PlatformCore_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/ICLK}
u_PlatformCore_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clk     1.07200   {0.00000 0.53600}   P,G         {U8/U1/mig_7series_0/u_PlatformCore_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK}
u_PlatformCore_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk     1.07200   {1.00500 1.54100}   P,G         {U8/U1/mig_7series_0/u_PlatformCore_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in/ICLK}
u_PlatformCore_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clk     1.07200   {0.00000 0.53600}   P,G         {U8/U1/mig_7series_0/u_PlatformCore_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK}
u_PlatformCore_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk     1.07200   {1.00500 1.54100}   P,G         {U8/U1/mig_7series_0/u_PlatformCore_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK}
u_PlatformCore_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/oserdes_clk     1.07200   {0.00000 0.53600}   P,G         {U8/U1/mig_7series_0/u_PlatformCore_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK}
u_PlatformCore_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk     1.07200   {1.00500 1.54100}   P,G         {U8/U1/mig_7series_0/u_PlatformCore_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK}
u_PlatformCore_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clk     1.07200   {0.00000 0.53600}   P,G         {U8/U1/mig_7series_0/u_PlatformCore_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK}
u_PlatformCore_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clk     1.07200   {0.00000 0.53600}   P,G         {U8/U1/mig_7series_0/u_PlatformCore_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK}
u_PlatformCore_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/oserdes_clk     1.07200   {0.00000 0.53600}   P,G         {U8/U1/mig_7series_0/u_PlatformCore_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK}
u_PlatformCore_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clk     1.07200   {0.00000 0.53600}   P,G         {U8/U1/mig_7series_0/u_PlatformCore_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK}
u_PlatformCore_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk     1.07200   {1.00500 1.54100}   P,G         {U8/U1/mig_7series_0/u_PlatformCore_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in/ICLK}
u_PlatformCore_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clk     1.07200   {0.00000 0.53600}   P,G         {U8/U1/mig_7series_0/u_PlatformCore_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK}
u_PlatformCore_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk     1.07200   {1.00500 1.54100}   P,G         {U8/U1/mig_7series_0/u_PlatformCore_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in/ICLK}
u_PlatformCore_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clk     1.07200   {0.00000 0.53600}   P,G         {U8/U1/mig_7series_0/u_PlatformCore_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK}
u_PlatformCore_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk     1.07200   {1.00500 1.54100}   P,G         {U8/U1/mig_7series_0/u_PlatformCore_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK}
u_PlatformCore_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/oserdes_clk     1.07200   {0.00000 0.53600}   P,G         {U8/U1/mig_7series_0/u_PlatformCore_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK}
u_PlatformCore_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk     1.07200   {1.00500 1.54100}   P,G         {U8/U1/mig_7series_0/u_PlatformCore_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK}
u_PlatformCore_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clk     1.07200   {0.00000 0.53600}   P,G         {U8/U1/mig_7series_0/u_PlatformCore_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK}
u_PlatformCore_mig_7series_0_0_mig/u_ddr3_infrastructure/clk_pll_i                                                                                                                               4.28800   {0.00000 2.14400}   P,G         {U8/U1/mig_7series_0/u_PlatformCore_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT}
u_PlatformCore_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clkout0                                                                                                                            85.76000  {0.00000 42.88000}  P,G         {U8/U1/mig_7series_0/u_PlatformCore_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT0}
u_PlatformCore_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clkout1                                                                                                                            8.57600   {0.00000 4.28800}   P,G         {U8/U1/mig_7series_0/u_PlatformCore_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT1}
u_PlatformCore_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clkout2                                                                                                                            17.15200  {0.00000 8.57600}   P,G         {U8/U1/mig_7series_0/u_PlatformCore_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT2}

 

Is there a way (constraint) to rename auto-generated clocks such that I see short meaningful names in the clock report and such that I can derive other constraints from those meaningful names?

 

Thanks!

 

Claude

 

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Guide avrumw
Guide
23,739 Views
Registered: ‎01-23-2009

Re: TCL/XDC: Renaming clocks

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In UG903 (v2013.4 p.66) there is a section "Renaming Auto-Derived Clocks", which shows the command

 

create_generated_clock -name new_name [-source master_pin] [-master_clock master_clk] source_object

 

(the [] are optional parameters, not commands - you don't normally need -source and -master)

 

The "source object" should be the same object that is used as the source of the auto-derived clock. So for your CLKOUT0 clock you would use

 

create_generated_clock -name my_clkout0 [get_pins U7/clk_wiz_0/U0/plle2_adv_inst/CLKOUT0]

 

Another alternative is not to rename the clock, but to just use a variable instead. You can do the same thing with

 

set my_clkout0 [get_clocks -of_objects [get_pins U7/clk_wiz_0/U0/plle2_adv_inst/CLKOUT0]]

 

Now you can use $my_clkout0 wherever you need that clock.

 

Avrum

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2 Replies
Highlighted
Guide avrumw
Guide
23,740 Views
Registered: ‎01-23-2009

Re: TCL/XDC: Renaming clocks

Jump to solution

In UG903 (v2013.4 p.66) there is a section "Renaming Auto-Derived Clocks", which shows the command

 

create_generated_clock -name new_name [-source master_pin] [-master_clock master_clk] source_object

 

(the [] are optional parameters, not commands - you don't normally need -source and -master)

 

The "source object" should be the same object that is used as the source of the auto-derived clock. So for your CLKOUT0 clock you would use

 

create_generated_clock -name my_clkout0 [get_pins U7/clk_wiz_0/U0/plle2_adv_inst/CLKOUT0]

 

Another alternative is not to rename the clock, but to just use a variable instead. You can do the same thing with

 

set my_clkout0 [get_clocks -of_objects [get_pins U7/clk_wiz_0/U0/plle2_adv_inst/CLKOUT0]]

 

Now you can use $my_clkout0 wherever you need that clock.

 

Avrum

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Scholar chevalier
Scholar
14,146 Views
Registered: ‎10-07-2011

Re: TCL/XDC: Renaming clocks

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Avrum,

 

Many thanks. Another very valuable reply, as always!

 

Claude

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