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Observer strauman
Observer
1,393 Views
Registered: ‎01-23-2017

Unable to use 'create_debug_port' in 2017.3

I have a project with a debug bridge in jtag-BSCAN mode. I know that previous versions of vivado did't support debug insertion in this mode. However, I has happy to find that in 2017.3 I can open the synthesized design, then

create_debug_core ila1 ila

 

without errors. I can also connect a clock, configure probe0's width and connect that probe to nets and implement the design successfully.

 

However, the attempt to add more probes

 

create_debug_port ila1 probe

 

still fails with

 

ERROR: [Common 17-69] Command failed: This design contains a debug_bridge IP configured in either 'From_AXI_to_BSCAN' or 'From_JTAG_to_BSCAN' mode. Debug insertion is not currently supported for such designs. Please use the debug instantiation flow.

 

Does this restriction still apply? Even though inserting a debug core with a single port works?

 

Thanks for clarifying

- Till

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2 Replies
Xilinx Employee
Xilinx Employee
1,375 Views
Registered: ‎08-01-2008

Re: Unable to use 'create_debug_port' in 2017.3

This can happen if you generate an IP core with an evaluation license and then purchase or install a full license but do not regenerate the IP core.

When the IP core is generated, the license information is stored in the netlist file and it stays in the netlist file even after you change the license to something else.

If the output products are not updated, then the old license will still be pointed to even after a valid license is installed.

The IP core needs to be generated or re-generated on a machine with access to the full license.

 

To fix this issue, follow the steps below:

  1. In the Project Manager Window click on the IP sources tab.
  2. Select all IP that were affected by the newly installed IP license.
  3. Right click on the IP and click Reset Output Products.
  4. Select all IP that were affected by the newly installed IP license again.
  5. Right click on the IP and click Generate Output Products.
  6. This will update the netlist file with the new valid license file information.
  7. Generate bitstream.

 

You can check the license status for the IP core that is failing by using a Tcl script similar to the following.

set dp_ips [get_cells -hierarchical {displayport*}]

foreach ips $dp_ips {report_property $ips}

Here is an example output:

  core_generation_info           string  false      design_1_displayport_0_0,design_1_displayport_0_0_dport_wrapper,
{x_ipProduct=Vivado 2013.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=displayport,x_ipVersion=4.1,
x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipLicense=displayport@2013.10(design_linking),
C_COMPONENT_NAME=design_1_displayport_0_0,C_FAMILY=kintex7,
C_FLOW_DIRECTION=1,C_LANE_COUNT=4,C_INCLUDE_HDCP=0,C_SECONDARY_SUPPORT=0,
C_AUDIO_CHANNELS=2,C_IEEE_OUI=000A35,C_VENDOR_SPECIFIC=0,C_PROTOCOL_SELECTION=1,
C_LINK_RATE=20,C_MST_ENABLE=0,C_NUMBER_OF_MST_STREAMS=2,C_MAX_BITS_PER_COLOR=16,
C_QUAD_PIXEL_ENABLE=0,C_DUAL_PIXEL_ENABLE=1,C_YCRCB_ENABLE=1,C_YONLY_ENABLE=0}

 

If your IP core is part of the IP Integrator Subsystem (Block Design), then you will need to force a clearing of all the IPI outputs and regenerate.

Thanks and Regards
Balkrishan
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Observer strauman
Observer
1,323 Views
Registered: ‎01-23-2017

Re: Unable to use 'create_debug_port' in 2017.3

Hmm.

 

Frankly, I doubt that this is the reason - I added the debug core from tcl to a synthesized design. The operation returns quickly and no IP has been generated yet.

 

I suspect a bug in create_debug_port - probably the check for the presence of an Jtag to BSCAN bridge (which was necessary under previous versions of vivado which would return the same error message from create_debug_core also) was not removed.

 

FWIW I tried to retrieve the info you suggested - the closest I could do was

 

 

Vivado% open_run synth_1

Vivado% create_debug_core myila ila myila Vivado% report_property [get_cells myila] Property Type Read-only Value CLASS string true cell CORE_GENERATION_INFO string true myila,labtools_ila_v6_00_a,{ALL_PROBE_SAME_MU=true,ALL_PROBE_SAME_MU_CNT=1,C_ADV_TRIGGER=false,C_DATA_DEPTH=1024,C_EN_STRG_QUAL=false,C_INPUT_PIPE_STAGES=0,C_NUM_OF_PROBES=1,C_PROBE0_TYPE=0,C_PROBE0_WIDTH=1,C_TRIGIN_EN=0,C_TRIGOUT_EN=0,component_name=myila_CV} DONT_TOUCH bool false 1 IS_BLACKBOX bool true 1 IS_DEBUGGABLE bool true 1 IS_DEBUG_CORE bool true 1 IS_MATCHED bool true 0 IS_ORIG_CELL bool true 0 IS_PRIMITIVE bool true 0 IS_REUSED bool true 0 IS_SEQUENTIAL bool true 0 NAME string true myila PRIMITIVE_COUNT int true 1 REF_NAME string true myila_CV REUSE_STATUS enum true

There is no licensing information in the core_generation_info - and the core has not even been generated yet (plus, iirc, no special license is required for instantiating an ila core).

 

However,

Vivado% create_debug_port 
ERROR: [Common 17-69] Command failed: This design contains a debug_bridge IP configured in either 'From_AXI_to_BSCAN' or 'From_JTAG_to_BSCAN' mode. Debug insertion is not currently supported for such designs. Please use the debug instantiation flow.

fails - note that it fails even *before* I told it on what core I wanted to create a port (it would fail with the identical message if I provide 'good' arguments. Thus it seems like an early argument check - however, the fact that I can use the first probe which is generated by default as a result of create_debug_core without problems indicates that 2017.3 indeed would support the debug insertion flow.

 

Here is an attempt with valid arguments

Vivado% create_debug_port myila probe
ERROR: [Common 17-69] Command failed: This design contains a debug_bridge IP configured in either 'From_AXI_to_BSCAN' or 'From_JTAG_to_BSCAN' mode. Debug insertion is not currently supported for such designs. Please use the debug instantiation flow.
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