We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Visitor aspenlogic
Registered: ‎08-01-2014

Using Vivado TCL command show_schematic on the root of the design


I was looking for a scriptable way to generate the top schematic after running a script.


I find it curious that show_schematic requires an object but no command will return the object for the root of the design. I expected either show_schematic with no argument (or the empty string {}) should show the schematic for the current instance (as reported by current_instance) when it is the root or there should be a command like get_cells / that returns an object for the root..



Hence, to view the top level of the design, UG835's entry for show_schematic indicates that the TCL command show_schematic [get_nets] is required. This works but seems counter-intuitive. Not to mention non-orthogonal when you consider that show_schematic [get_cells pcie_interface/transaction/ctr] would show the schematic for that instance path in the design. Meaning show_schematic [get_cells /] should work as expected to show the schematic for the top level (using a conventional indication of a solitary slash as the root.)




I have that now, yet my curiosity as to why get_cells / does not work as expected is unsatisfied.


Any thought leaders out there have an explanation of this (apparent) inconsistency?


What am I missing here?


Is there a subtlety to wanting all instances paths to be relative to avoid giving meaning to a leading slash?


Why doesn't show_schematic [current_instance] work when the current instance is the top of the netlist/design?



For those reading this post, try

show_schematic [get_pins]
show_schematic [get_ports]
show_schematic [get_cells]

The first two produce surprisingly useful pictures. The last one appears to produce a schematic of the entire design. Yet, in some cases nets were not completely rendered and ports were missing!

By: Timothy R Davis, President
0 Kudos