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Visitor
Visitor
1,159 Views
Registered: ‎07-23-2018

VHDL Conditional compilation

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Hi,

Can we have conditional compilation (build differs in logic and I/O pin mapping) as a single fpga configuration file.

FPGA Family: Artyx 7

Coding : VHDL

I have used the conditional compilation technique (which differs in logic using 'ifdef) in verilog. Since VHDL doesnt have maro-languages, how can we implement the same.

Many Thanks

Sruthi

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Scholar
Scholar
972 Views
Registered: ‎08-01-2012

If you want a different pinout you can import the XDC as unmanaged and then you can include any tcl in it. Note. Vivado cannot modify unmanaged tcl files.

If {$variant eq "variantA" } {
  #pins for variant a
} else {
  #pins for variant b
}

This along with generics allows you to easily control what you're building.  I highly recommend scripting your build flow,  then you can easily choose what to build from the command line.

 

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Teacher
Teacher
1,141 Views
Registered: ‎07-09-2009
You cant ,

A configuration file defines the working of the FPGA,
the configuration file is made from your HDL,

so if you change the HDL you get a different configuration file.
no matter if you do that in VHDL or Sverilog or Python et all,

There is the option in FPGAs to have multi boot,
but that's a different thing to what your describing using #defines.
many example son the web, but this gives you the idea

https://www.xilinx.com/support/documentation/application_notes/xapp1257-multiboot-fallback-spi-flash.pdf

And what do you want to do in a macro language in VHDL ?


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Highlighted
Scholar
Scholar
1,111 Views
Registered: ‎08-01-2012

You can use generics and generates to specify what exist inside an FPGA build

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Visitor
Visitor
1,085 Views
Registered: ‎07-23-2018

Please confirm can we use the same method even if few I/O pin differs..

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Visitor
Visitor
1,079 Views
Registered: ‎07-23-2018

I am not trying for the multiboot option in FPGA, instead i need a conditional compilation(both RTL and xdc file) technique.

I have tried conditional compilation in verilog RTL code using  'ifdef as in below syntax .

`ifdef <FLAG1>
       // Statements
`elsif <FLAG2>
      // Statements
`else
     // Statements
`endif

Please advice is it possible to achieve the same logic in VHDL. 

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Teacher
Teacher
1,063 Views
Registered: ‎07-09-2009
The equivalent in VHDL is
If generate / else generate

ensure you have 2008 turned on

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
Highlighted
Scholar
Scholar
973 Views
Registered: ‎08-01-2012

If you want a different pinout you can import the XDC as unmanaged and then you can include any tcl in it. Note. Vivado cannot modify unmanaged tcl files.

If {$variant eq "variantA" } {
  #pins for variant a
} else {
  #pins for variant b
}

This along with generics allows you to easily control what you're building.  I highly recommend scripting your build flow,  then you can easily choose what to build from the command line.

 

View solution in original post

Highlighted
Teacher
Teacher
938 Views
Registered: ‎07-09-2009
With tkl you can do anything,

but

You still cant have two different designs in the one configuration file which is what you asked for.

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Contributor
Contributor
727 Views
Registered: ‎06-23-2018

Hi,

The following code maybe help you:

LABEL_Simulation_Only_IO:
if (Report_Enable_IO = '1') generate
begin

Report_Unit_1 : Report_Unit
generic Map(
...
) 
Port Map(
...
);

end generate;
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