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morlior.deep
Visitor
Visitor
812 Views
Registered: ‎07-18-2019

Vitis - U250 - Generate RTL Kernel via command line - package_project fails

Hi,

I'm using Vitis (with Vivado 2019.2) in order to produce an xclbin file from synthesis and so.

I've created a Vitis then Vivado "empty application" project with my needs of 4x AXI. I've added my V code files to the Vivado project in the GUI.

I've succeedded to generte RTL kernel via GUI, then producing xclbin file back in Vitis GUI.

1.

Now, in order to do this with updated code files, from command line, with tcl - I've tried to repeat the same tcl commands from the Vivado generating RTL kernel process, and by almost the end of "package_project" run, it fails and it's written:

ERROR: [Common 17-161] Invalid option value '' specified for 'objects'.
INFO: [Common 17-206] Exiting Vivado at Wed Mar 11 20:22:01 2020...

Then no xo file is being generated, and the whole Vitis xclbin producing can't start.

If I try to do the commands, one by one the same in the GUI tcl console, everything works well.

 

What do I lack?

 

2. Another Issue, that in the beginning of the "package_project" process, it's written that many of my Verilog code files are not being packaged, because they are unreferenced from the top module: 

WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/ubuntu/workspace/vitis_kernel_wizard_1/vivado_rtl_kernel/vivado_rtl_kernel.srcs/sources_1/ip/rtl_kernel_wizard_1/rtl_kernel_wizard_1.xci'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/vitis_src/axi_infrastructure_v1_1_0.vh'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: /vitis_src/rtl_kernel_wizard_1.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: ......
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: ......
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: ......
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged:

 

And so many on..

I've set correctly the top file, they all do referenced in the top and down.. Also it works via GUI "generate RTL kernel" process..

What can be the problem?

 

Thank you so much for your help.

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1 Reply
romisaas
Xilinx Employee
Xilinx Employee
674 Views
Registered: ‎02-12-2020

Hi @morlior.deep ,

For the First question

For the Second question

Please let me know if you still need more assistance.


Thanks,
-Romisaa
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