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Visitor jeremy.roy
Visitor
5,131 Views
Registered: ‎11-02-2016

Vivado 2016.3 Block design with rtl module in non-project

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Hi there,

 

I am currently using Vivado 2016.2 in non-project mode.  Recently I tried to import a block-design containing an RTL module reference.  When I tried to import the block-design tcl into the non-project mode project, I got the following error:

 

set block_name foo
set block_cell_name foo
create_bd_cell -type module -reference $block_name $block_cell_name
CRITICAL WARNING: [filemgmt 56-176] Module references are not supported in manual compile order mode and will be ignored.
ERROR: [filemgmt 56-189] Failed to resolve reference. Nothing was found in the project to match the name 'foo'.
ERROR: [BD 41-1690] Unable to resolve module-source based on inputs: foo
ERROR: [BD 5-7] Error: running create_bd_cell  -type module -reference foo -name foo .
ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.

I was wondering why non-project mode doesn't support RTL modules (is there a good reason?), and if Vivado 2016.3 has support for RTL modules in non-project mode?

 

Thanks for the help!

 

-J

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Xilinx Employee
Xilinx Employee
9,415 Views
Registered: ‎09-20-2012

Re: Vivado 2016.3 Block design with rtl module in non-project

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Hi @jeremy.roy

 

Please add the following project property prior reading in the sources, then the module reference would be resolved and synthesis will run successfully:
set_property source_mgmt_mode All [current_project]

Thanks,
Deepika.
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Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
3 Replies
Visitor jeremy.roy
Visitor
5,106 Views
Registered: ‎11-02-2016

Re: Vivado 2016.3 Block design with rtl module in non-project

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Newbie mistake: posted this to the wrong community.  Can a moderator move this to Vivado TCL Community?  Thanks!

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Xilinx Employee
Xilinx Employee
9,416 Views
Registered: ‎09-20-2012

Re: Vivado 2016.3 Block design with rtl module in non-project

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Hi @jeremy.roy

 

Please add the following project property prior reading in the sources, then the module reference would be resolved and synthesis will run successfully:
set_property source_mgmt_mode All [current_project]

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
Highlighted
2,211 Views
Registered: ‎01-11-2018

Re: Vivado 2016.3 Block design with rtl module in non-project

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I followed the instructions in the below link to resolve this issue:

 

https://www.xilinx.com/support/answers/63488.html

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